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    MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN
    162.
    发明专利
    MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN 未知

    公开(公告)号：CA3049454A1

    公开(公告)日：2018-08-09

    申请号：CA3049454

    申请日：2018-01-19

    Applicant: QUALCOMM INC

    Inventor： SORIAGA JOSEPH BINAMIRA ,  SARKIS GABI ,  KUDEKAR SHRINIVAS ,  RICHARDSON THOMAS ,  LONCKE VINCENT

    IPC: H03M13/03 ,  H03M13/00 ,  H03M13/11

    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.

    CONFIGURABLE COMMON UPLINK BURST LENGTH
    163.
    发明专利
    CONFIGURABLE COMMON UPLINK BURST LENGTH 未知

    公开(公告)号：CA3047150A1

    公开(公告)日：2018-07-19

    申请号：CA3047150

    申请日：2018-01-12

    Applicant: QUALCOMM INC

    Inventor： ZENG WEI ,  JI TINGFANG ,  SORIAGA JOSEPH BINAMIRA

    IPC: H04L5/14

    Abstract: Various aspects are provided for dynamic configuration of common uplink bursts. For example, the described apparatus and methods include receiving, at a user equipment (UE), an indicator of a length of a common uplink burst from a gNB, configuring the common uplink burst having the length as identified by the indicator, and transmitting, from the UE, the common uplink burst to the gNB.

    Flexible transmission unit and acknowledgment feedback timeline for efficient low latency communication
    165.
    发明专利
    Flexible transmission unit and acknowledgment feedback timeline for efficient low latency communication 未知

    公开(公告)号：AU2016366308A1

    公开(公告)日：2018-05-24

    申请号：AU2016366308

    申请日：2016-12-09

    Applicant: QUALCOMM INC

    Inventor： MUKKAVILLI KRISHNA KIRAN ,  JIANG JING ,  LUO TAO ,  JI TINGFANG ,  ANG PETER PUI LOK ,  SORIAGA JOSEPH BINAMIRA

    IPC: H04L1/18 ,  H04L1/00 ,  H04L1/16

    Abstract: Certain aspects relate to methods and apparatus for a flexible transmission unit and acknowledgement feedback timeline for low-latency communication. As described herein, a UE may receive, within a subframe a first portion of a downlink control region scheduling at least a first data unit, wherein the subframe comprises at least two TTIs and wherein the subframe comprises the downlink control region, a data region, and an uplink control region, receive the first data unit in a first TTI of the data region, receive a second data unit in a second TTI of the data region, and separately acknowledge receipt of the first and second data units. According to aspects, the acknowledgment for the first data unit may occur in the same subframe as the transmission of the first data unit. A BS may perform corresponding operations.

    Estructura de trama unificada
    167.
    发明专利
    Estructura de trama unificada 未知

    公开(公告)号：CL2017001031A1

    公开(公告)日：2017-12-22

    申请号：CL2017001031

    申请日：2017-04-26

    Applicant: QUALCOMM INC

    Inventor： BHUSHAN NAGA ,  JI TINGFANG ,  SMEE JOHN EDWARD ,  SORIAGA JOSEPH BINAMIRA ,  MUKKAVILLI KRISHNA KIRAN ,  AZARIAN YAZDI KAMBIZ ,  JIANG JING ,  ANG PETER PUI LOK

    IPC: H04L27/26

    Abstract: UN DISEÑO DE ESTRUCTURA DE TRAMA UNIFICADA INCLUYE MÚLTIPLES ESTRUCTURAS PARA SOPORTAR MÚLTIPLES REQUERIMIENTOS DE ACCESO; EN ALGUNOS ASPECTOS, DIFERENTES REQUERIMIENTOS DE ACCESO SE PUEDEN RELACIONAR CON DIFERENTES CATEGORÍAS DE TERMINAL DE ACCESO Y/O DIFERENTES APLICACIONES; EN ALGUNOS ASPECTOS, DIFERENTES CATEGORÍAS DE TERMINAL DE ACCESO SE PUEDEN RELACIONAR CON DIFERENTES REQUERIMIENTOS DE RENDIMIENTO DE DIFERENTES TERMINALES DE ACCESO, EN ALGUNOS ASPECTOS, EL DISEÑO DE LA ESTRUCTURA DE TRAMA UNIFICADA DIVULGADA PODRÍA SOPORTAR, POR EJEMPLO, Y SIN LIMITACIÓN, AL MENOS UNO DE: UN MODO DE BAJA LATENCIA, UN MODO DE BAJA SOBRECARGA, UN MODO DE BAJA POTENCIA (POR EJEMPLO, PARA MICRO-DORMIR Y/O CONMUTACIÓN DE ANCHO DE BANDA DINÁMICO), UNA TERMINAL DE ACCESO CON CAPACIDAD DE BANDA ANGOSTA QUE OPERA EN BANDA ANCHA, O LATENCIA ULTRA-BAJA Y MULTIPLEXIÓN NOMINAL; TAMBIÉN SE RECLAMAN Y DESCRIBEN OTROS ASPECTOS, MODALIDADES Y CARACTERÍSTICAS.

    Scaled symbols for a self-contained time division duplex (TDD) subframe structure
    168.
    发明专利
    Scaled symbols for a self-contained time division duplex (TDD) subframe structure 未知

    公开(公告)号：AU2016265699A1

    公开(公告)日：2017-11-02

    申请号：AU2016265699

    申请日：2016-05-13

    Applicant: QUALCOMM INC

    Inventor： JI TINGFANG ,  SMEE JOHN EDWARD ,  SORIAGA JOSEPH BINAMIRA ,  MUKKAVILLI KRISHNA KIRAN ,  JIANG JING ,  ANG PETER PUI LOK

    IPC: H04L5/00 ,  H04L1/00 ,  H04L5/14

    Abstract: In an aspect of the disclosure, a method, a computer program product, and an apparatus are provided. The method may be performed by a scheduling entity. The scheduling entity transmits control information in a control portion of the subframe, the control information corresponding to data information within the subframe, transmits the data information in a data portion of the subframe, receives a pilot signal from the set of subordinate entities in a pilot portion of the subframe, and receives an ACK/NACK signal from the set of subordinate entities in an ACK portion of the subframe. The ACK portion is subsequent to the pilot portion of the subframe. The ACK/NACK signal includes acknowledgment information corresponding to the data information. The control portion, the data portion, the pilot portion, and the ACK portion are contained in the same subframe.

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