公开(公告)号：WO2012072726A1

公开(公告)日：2012-06-07

申请号：PCT/EP2011/071480

申请日：2011-12-01

Applicant: STMICROELECTRONICS S.R.L. ,  ZUFFADA, Maurizio ,  POZZONI, Massimo ,  CONTINI, Angelo

Inventor： ZUFFADA, Maurizio ,  POZZONI, Massimo ,  CONTINI, Angelo

IPC: H03F3/30 ,  H03F1/22 ,  H03F3/24 ,  H03F3/217 ,  H03F3/45 ,  H04B10/155 ,  H03K19/0185

CPC classification number: G02F1/0121 ,  G02B6/1225 ,  G02B2006/12142 ,  G02B2006/12145 ,  G02F1/0327 ,  G02F1/225 ,  G02F2001/212 ,  H03F1/22 ,  H03F1/223 ,  H03F3/2171 ,  H03F3/245 ,  H03F3/3001 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/45 ,  H03F2200/516 ,  H03F2203/30099 ,  H03F2203/30132 ,  H03K19/018528 ,  H04B10/532 ,  H04B10/616

Abstract: A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

Abstract translation: 驱动器电路可以包括第一节点（VA）和第一电路，用于在第一电源电压（Vdd1）和地之间的驱动器切换期间在第一节点（VA）上产生输入信号（VIN）的反相副本， 反转副本具有基于大于第一电源电压（Vdd1）的参考电压（Vref）的阈值电压值。 驱动器电路可以包括由参考电压（Vref）控制并耦合在第二电源电压（Vdd2）和第一节点之间的共源共栅级（M3），延迟电路（D）以产生延迟复制 输入信号（VIN），放大器和开关网络（M5，M6），用于将有源负载晶体管（M9）的控制端子耦合到参考电压（Vref）中的一个或接地，基于输入 信号（VIN）。

公开(公告)号：WO2011101393A1

公开(公告)日：2011-08-25

申请号：PCT/EP2011/052319

申请日：2011-02-16

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/544

CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A testing system for carrying out electrical testing of at least a through via (10) extending, at least in part, through a substrate (3) of a body (2) of semiconductor material and having a first end (10b) buried within the substrate (3) and not accessible from the outside of the body (2). The testing system has an electrical test circuit (22) integrated in the body (2) and electrically coupled to the through via (10) and to electrical-connection elements (8) carried by the body (2) for electrical connection towards the outside; the electrical test circuit (22) has a buried microelectronic structure (28) integrated in the substrate (3) so as to be electrically coupled to the first end (10b) of the through via (10), thereby closing an electrical path within the substrate (3) and enabling detection of at least one electrical parameter of the through via (10) through the electrical-connection means (8).

Abstract translation: 至少一个至少部分通过半导体材料的主体（2）的基板（3）延伸的通孔（10）进行电气测试的测试系统，并且具有埋在该半导体材料的第一端（10b）内的第一端 基板（3）并且不能从主体（2）的外部接近。 测试系统具有集成在主体（2）中并电耦合到通孔（10）的电测试电路（22）和由主体（2）承载的电连接元件（8），用于电连接到外部 ; 电测试电路（22）具有集成在基板（3）中的埋入微电子结构（28），以便电连接到通孔（10）的第一端（10b），从而封闭通孔 基板（3），并且能够通过电连接装置（8）检测通孔（10）的至少一个电参数。

公开(公告)号：WO2011073853A1

公开(公告)日：2011-06-23

申请号：PCT/IB2010/055632

申请日：2010-12-07

Applicant: STMICROELECTRONICS S.R.L. ,  ITALIA, Alessandro ,  DIMARTINA, Salvatore ,  IPPOLITO, Calogero Marco ,  PALMISANO, Giuseppe

Inventor： ITALIA, Alessandro ,  DIMARTINA, Salvatore ,  IPPOLITO, Calogero Marco ,  PALMISANO, Giuseppe

IPC: H03B5/12 ,  H03B1/00

CPC classification number: H03B5/1243 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1268 ,  H03B5/1296 ,  H03B2200/0038 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03B2201/0266 ,  Y10T29/49117

Abstract: Circuit (1) of a voltage controlled oscillator comprising: - a bridge structure including two cross-coupled transistors of N type (M 3 , M 4 ) and two cross-coupled transistors of P type (M 5 , M 6 ); - a current mirror (3) connected to the two cross-coupled transistors of N type (M 3 , M 4 ) and arranged to generate a bias current (I B ) for the circuit (1); - an LC resonator (2) placed in parallel between the two cross-coupled transistors of N type (M 3 , M 4 ) and the two cross-coupled transistors of P type (M 5 , M 6 ). The circuit (1) is characterised in that the LC resonator (2) comprises: two pairs of differential inductors (L 1 , L 2 ) mutually coupled by means of a mutual inductance coefficient (M), each pair comprising a first inductor (L 1 ) arranged on a respective branch (10a) of an external loop, and a second inductor (L 2 ) arranged on a respective branch (12a) of an internal loop; a first varactor (C v33 ) connected to a common node (A) and to a first branch (12a) of the internal loop; a second varactor (C v33 ) connected to the common node (A) and to a second branch (12a) of the internal loop.

Abstract translation: 压控振荡器的电路（1）包括： - 包括N型（M3，M4）的两个交叉耦合晶体管和P型（M5，M6）的两个交叉耦合晶体管的桥结构; - 连接到N型（M3，M4）的两个交叉耦合晶体管并被布置成产生用于电路（1）的偏置电流（IB））的电流镜（3）。 - 平行放置在N型（M3，M4）的两个交叉耦合晶体管和P型（M5，M6）的两个交叉耦合晶体管之间的LC谐振器（2）。 电路（1）的特征在于，LC谐振器（2）包括：通过互感系数（M）相互耦合的两对差分电感器（L1，L2），每对包括布置在第一电感器（L1） 在外部环路的相应分支（10a）上，以及布置在内部环路的相应分支（12a）上的第二电感器（L2） 连接到公共节点（A）和内部回路的第一分支（12a）的第一变容二极管（Cv33） 连接到公共节点（A）和第二分支（12a）的第二变容二极管（Cv33）。

公开(公告)号：WO2011063974A1

公开(公告)日：2011-06-03

申请号：PCT/EP2010/007185

申请日：2010-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  ROSSI, Sandro

IPC: H03K3/355

CPC classification number: H03K3/355

Abstract: It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first portion (2A) connected to a first voltage reference (VPH) and including at least one first output transistor (MOP) being inserted between the first voltage reference (VPH) and the output terminal (OUT), such a first portion (2A) further comprising: at least one first high voltage comparator (3A) being connected to said output terminal (OUT) and to a first threshold voltage reference (VTHP), at least one first start-up circuit (4A) being controlled by a first setting signal (SETP); at least one first switching ON /OFF circuit (5A) being connected at its input to the first start-up circuit (4A), in correspondence with a first internal circuit node (XP), and to the first high voltage comparator (3A), in correspondence with a second internal circuit node (YP), and at its output to a control terminal of the first output transistor (MOP); the first start-up circuit (4A) providing a switching on signal (ONA) to the first switching on/ off circuit (5A) while the high voltage comparator (3A) provides a switching off signal (OFFA) to the first switching on/ off circuit (5A) which causes the switching off of the output transistor (MOP), the high voltage comparator (3A) generating the switching off signal (OFFA) when the output voltage (Vout) reaches a first desired supply voltage value which depends on the value of the first threshold voltage reference (VTHP).

Abstract translation: 描述了具有连接到超声波脉冲发生器电路并向其提供输出电压（Vout）的至少一个输出端子（OUT）的驱动电路（1），其特征在于它包括至少一个连接的第一部分（2A） 至少一个第一输出晶体管（MOP）被插入在第一参考电压（VPH）和输出端子（OUT）之间，所述第一部分（2A）还包括：至少一个 第一高压比较器（3A）连接到所述输出端（OUT）和第一阈值电压基准（VTHP），至少一个第一启动电路（4A）由第一设置信号（SETP）控制; 至少一个第一开关ON / OFF电路（5A）在其输入端与第一内部电路节点（XP）相对应地连接到第一启动电路（4A），并连接到第一高电压比较器（3A） 对应于第二内部电路节点（YP），并且在其输出端与第一输出晶体管（MOP）的控制端相对应; 所述第一启动电路（4A）向所述第一开关导通/断开电路（5A）提供开启信号（ONA），同时所述高电压比较器（3A）向所述第一开关导通/断开电路提供断开信号（OFFA） 关闭电路（5A），当输出电压（Vout）达到第一期望的电源电压值时，高电压比较器（3A）产生关断信号（OFFA），导致关闭输出晶体管（MOP） 第一阈值电压基准值（VTHP）。

公开(公告)号：WO2010076687A1

公开(公告)日：2010-07-08

申请号：PCT/IB2009/055359

申请日：2009-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  RICCI, Raffaele

Inventor： RICCI, Raffaele

IPC: G01R31/28

CPC classification number: G01R31/002 ,  G01R31/2849

Abstract: In order to verify robustness in regard to electrical overstresses of an electronic circuit under test (DUT), the latter is exposed to electrical overstresses (12, 14), and the behaviour thereof following upon exposure to said electrical overstresses is monitored (18). Moreover, the electrical overstress is applied to the electronic circuit (DUT) when the electronic circuit (DUT) is in its normal applicational conditions of operation. In particular, there is envisaged both the testing of the electronic circuit (DUT) in dynamic conditions by causing it to be traversed by the currents that characterize operation thereof and by exposing at least one supply line (20) of said electronic circuit under test (DUT) to electrical overstresses and the testing of said electronic circuit under test (DUT) in static conditions, without causing it to be traversed by the currents that characterize operation thereof and by exposing to electrical overstresses both the supply (20) and the input and/or output lines of said electronic circuit under test (DUT). The device (14) for generating the overstresses can be mounted on a circuit board (12), which can be coupled as daughter board to a mother board (10), on which the electronic circuit under test (DUT) is mounted.

Abstract translation: 为了验证被测电子电路（DUT）的电应力的鲁棒性，后者被暴露于电过压（12,14），并且在暴露于所述电过应力之后监视其行为（18）。 此外，当电子电路（DUT）处于其正常的操作条件下时，电应力施加到电子电路（DUT）。 特别地，设想在动态条件下通过使其由表征其操作的电流穿过电子电路（DUT）并且通过暴露所测试的所述电子电路的至少一个供应线（20）来测试电子电路（DUT） DUT）在静态条件下进行电过载和测试所测试的被测电子电路（DUT），而不会使其被表征其操作的电流穿过，并暴露于对电源（20）和输入端的电过载 /或被测电子电路的输出线（DUT）。 用于产生过应力的装置（14）可以安装在电路板（12）上，该电路板可以作为子板耦合到母板（10），母板（10）上安装有被测电子电路（DUT）。

公开(公告)号：WO2010076189A1

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067167

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  ALESSI, Enrico ,  RICCERI, Daniele

Inventor： ALESSI, Enrico ,  RICCERI, Daniele

IPC: C12Q1/68

CPC classification number: C12Q1/6837 ,  C12Q1/6844 ,  C12Q1/686 ,  C12Q2527/101 ,  C12Q2561/113 ,  C12Q2527/107

Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (T H ) of the probes (37) is higher than an annealing temperature (T A ) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (R H , R A ).

Abstract translation: 一种用于进行核酸扩增的方法，包括提供在相应位置容纳核酸探针（37）的阵列（36）的反应室（31），用于与各自的靶核酸杂交; 以及将溶液（50）引入所述反应室（31）中，其中所述溶液（50）含有能够结合靶核酸，核苷酸，核酸延伸酶和包含核酸的样品的引物。 核酸探针（37）的结构和引物的结构使得探针（37）的杂交温度（TH）高于引物的退火温度（TA），由此在各自的条件下进行杂交和退火 分开的温度范围（RH，RA）。

公开(公告)号：WO2010057808A1

公开(公告)日：2010-05-27

申请号：PCT/EP2009/064918

申请日：2009-11-10

Applicant: STMicroelectronics (GRENOBLE) SAS ,  STMicroelectronics S.r.l. ,  COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

Inventor： COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

IPC: H01L25/16 ,  H01L23/538 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/0401

Abstract: A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

Abstract translation: 半导体器件包括至少一个第一部件（5）（例如，第一集成电路），其具有设置有电连接焊盘的正面。 第一部件嵌入在支撑层（2）中，是使得第一部件的前表面不被覆盖并平行于支撑层的第一面的位置。 在第一部件的正面和支撑层的第一面上形成中间层（8）。 中间层内的电连接网络（9）选择性地连接到第一部件的电连接焊盘。 该装置还包括至少一个第二部件（11）（例如，第二集成电路，其中一个面放置在中间层的上方，并且具有选择性地连接到电连接网络的电连接焊盘）。电连接通孔（17）通过 通过支撑层并且将电连接网络选择性地连接到形成在支撑层的第二面上的外部电连接。

公开(公告)号：WO2009080760A1

公开(公告)日：2009-07-02

申请号：PCT/EP2008/068047

申请日：2008-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: G01R1/073

CPC classification number: G01R31/2889 ,  B62M25/04 ,  G01R1/0491 ,  G01R1/06727 ,  G01R1/07342

Abstract: A probe card (105') adapted for testing at least one integrated circuit integrated on corresponding at least one die (145) of a semiconductor material wafer, the probe card including a board (125') adapted for the coupling to a tester apparatus, and a plurality of probes (225) coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units (135'), each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test (145), the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract translation: 一种探针卡（105'），适用于测试集成在半导体材料晶片的相应的至少一个管芯（145）上的至少一个集成电路，所述探针卡包括适于耦合到测试仪器的板（125'）， 以及耦合到所述板的多个探针（225），其中所述探针卡包括多个可更换的基本单元（135'），每个所述探针卡包括至少一个所述探针，用于接触集成电路的外部可接近的端子 所述多个可更换基本单元被布置成对应于包含要测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

公开(公告)号：WO2008136028A1

公开(公告)日：2008-11-13

申请号：PCT/IT2007/000338

申请日：2007-05-08

Applicant: STMICROELECTRONICS S.R.L. ,  TORAZZINA, Aldo ,  RUSSO, Riccardo

Inventor： TORAZZINA, Aldo ,  RUSSO, Riccardo

IPC: H04L12/10

CPC classification number: G01R27/08 ,  G06F1/26 ,  H04L12/10

Abstract: PDs that can be supplied through the LAN line are discriminated from PDs that cannot be so supplied in function of the resistance of the supply line and of the voltage drop Vdrop caused by nonlinear elements in series therewith. The values of these two parameters are estimated by applying two distinct voltages to the supply terminals of the LAN line and sensing the relative steady-state currents absorbed by the power supply line and by processing voltage and current values for estimating the resistance (Rdet) of the line and the voltage drop (Vdrop) caused by nonlinear elements connected in series therewith.

Abstract translation: 可以通过LAN线提供的PD与由供应线的电阻和由与其串联的非线性元件引起的电压降Vdrop不能如此提供的PD进行区分。 通过将两个不同的电压施加到LAN线路的电源端子并且感测由电源线吸收的相对稳态电流以及通过处理电压和电流值来估计这两个参数的值来估计电阻（Rdet）的电阻 由与串联连接的非线性元件引起的线路和电压降（Vdrop）。

公开(公告)号：WO2008012845A1

公开(公告)日：2008-01-31

申请号：PCT/IT2006/000575

申请日：2006-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  CONOCI, Sabrina ,  PETRALIA, Salvatore ,  SORTINO, Salvatore

Inventor： CONOCI, Sabrina ,  PETRALIA, Salvatore ,  SORTINO, Salvatore

IPC: C01B21/24 ,  A61K33/00 ,  B01J19/12

CPC classification number: C07C211/52 ,  A61K31/04 ,  A61K33/00 ,  B01J19/123 ,  B01J2219/089 ,  C01B21/24 ,  C07C323/29 ,  A61K2300/00

Abstract: The present invention- relates to the use of a nitroaniline derivative of Formula I for the production of nitric oxide and for the preparation of a medicament for the treatment of a disease wherein the administration of nitric oxide is beneficial. The present invention furthermore relates to a method for the production of NO irradiating a nitroaniline derivative of Formula I, a kit comprising a nitroaniline derivative of Formula I and a carrier and to a system comprising a source of radiations and a container associated to a nitroaniline derivative of Formula I. In Formula I, R and R I are each independently hydrogen or a C 1 -C 3 alkyl group; R II is hydrogen or an alkyl group.

Abstract translation: 本发明涉及式I的硝基苯胺衍生物在制备一氧化氮中的用途，以及制备用于治疗一氧化氮是有益的疾病的药物的用途。 本发明还涉及一种用于制备辐射式I的硝基苯胺衍生物的NO的方法，该试剂盒包含式I的硝基苯胺衍生物和载体，以及包含辐射源和与硝基苯胺衍生物相关的容器的体系 在式I中，R 1和R 2各自独立地为氢或C 1 -C 3烷基; R II是氢或烷基。