公开(公告)号：EP1442480B1

公开(公告)日：2019-03-06

申请号：EP02785549.3

申请日：2002-10-15

Applicant: 3D Plus

Inventor： VAL, Christian, Thales Int. Prop.

IPC: B81B7/00 ,  H01L23/10 ,  H01L23/31 ,  H01L23/34 ,  H01L31/0203 ,  H01L31/024 ,  G02B6/42

公开(公告)号：EP1256132B1

公开(公告)日：2018-05-09

申请号：EP01905860.1

申请日：2001-01-30

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L25/10 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

公开(公告)号：EP2441088B1

公开(公告)日：2016-07-20

申请号：EP10725161.3

申请日：2010-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

公开(公告)号：EP2054929B1

公开(公告)日：2016-03-16

申请号：EP07788221.5

申请日：2007-08-03

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/683 ,  H01L21/66 ,  H01L21/56 ,  H01L25/065 ,  H01L21/98

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/1461 ,  Y10T29/49004 ,  H01L2924/00

公开(公告)号：EP1966825B1

公开(公告)日：2009-10-21

申请号：EP06841479.6

申请日：2006-12-19

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/48 ,  H01L21/98 ,  H01L25/065

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D modules. It comprises a step of fabricating a batch of n wafers i on one and the same plate, this step being repeated K times, then a step of stacking the K plates, a step of forming plated-through holes in the thickness of the stack, these holes being intended for connecting the slices together, and then a step of cutting the stack in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2' placed on said face. After the stacking operation, holes are drilled perpendicular to the faces of the plates vertically in line with the grooves. The size of the holes is smaller than that of the grooves so that the silicon of each wafer 10 is isolated from the wall of the hole by resin.

公开(公告)号：EP1238431A1

公开(公告)日：2002-09-11

申请号：EP00993460.5

申请日：2000-12-12

Applicant: 3D Plus

Inventor： Val, Christian Thales Intellectual Property

IPC: H01L25/065 ,  H01L23/522 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L23/5222 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/184 ,  H05K1/185 ,  H05K3/045 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/10643 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/00

Abstract: The invention relates to a method and a device for interconnecting electronic components in three dimensions. In order to reduce the stray capacities between the connections and the shielding (304) of the device, metallized (42) grooves (40, 41) are cut into the block (3') of stacked circuits, the conductors (21) of said circuit being set back from the corresponding face (302) of the block. Said grooves cut into the connection conductors (21). The assembly is then coated with resin (303) and shielded by metallization (304). The invention is especially suitable for producing more compact three-dimensional electronic systems.

公开(公告)号：EP3905325A1

公开(公告)日：2021-11-03

申请号：EP21170597.5

申请日：2021-04-27

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L23/498

Abstract: L'invention se situe dans le domaine de la fabrication de modules électroniques 3D, compatible des composants fonctionnant au-delà de 1 GHz. L'invention concerne un module électronique 3D présentant une interconnexion entre un conducteur horizontal (31, 32 ; 33, 34) et un conducteur vertical (30) auquel il est relié présente dans un plan vertical une courbure non nulle. Elle concerne aussi le procédé de fabrication associé.

公开(公告)号：EP3417481B1

公开(公告)日：2020-03-25

申请号：EP17704275.1

申请日：2017-02-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L25/065 ,  H01L21/98 ,  H01L23/49 ,  H01L21/60 ,  H01L23/66

公开(公告)号：EP3417481A1

公开(公告)日：2018-12-26

申请号：EP17704275.1

申请日：2017-02-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L25/065 ,  H01L23/49 ,  H01L21/60

Abstract: The invention relates to a 3D electronic module comprising, along a so-called vertical direction, a stack (4) of electronic slices (16), each slice comprising at least one chip (1) furnished with interconnection pads (10), this stack being assembled to an interconnection circuit (2) of the module furnished with connection balls, the pads (10) of each chip being connected by electrical wiring leads (15) to vertical buses (41) that are in turn electrically linked to the module interconnection circuit (2), a wiring lead and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnection circuit, characterized in that each electrical wiring lead (15) is linked to its vertical bus (41) while forming an oblique angle (α2) in a vertical plane and in that the length of the wiring lead between a pad of a chip of one slice and the corresponding vertical bus is different from the length of the wiring lead between the same pad of a chip of another slice and the corresponding vertical bus, obtained by a non-rectilinear wiring of the wiring lead so as to compensate for the difference in vertical length of the vertical bus from slice to slice, in such a way that the electrical conductor between the pad of a chip of a slice and the interconnection circuit, and the electrical conductor between the same pad of a chip of the other slice and the interconnection circuit, have the same length.

公开(公告)号：EP3261116A1

公开(公告)日：2017-12-27

申请号：EP17175943.4

申请日：2017-06-14

Applicant: 3D Plus

Inventor： VAL, Christian

IPC: H01L21/56 ,  H01L23/31 ,  H01L25/03 ,  H01L25/10

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/142 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3511 ,  H05K3/321 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00

Abstract: L'invention a pour objet un procédé de fabrication collective de modules électroniques 3D, chaque module électronique 3D comprenant un empilement d'au moins deux boîtiers électroniques à billes, reportables en surface, testés à leur température et fréquence de fonctionnement. Il comprend :
- une étape de fabrication de plaques reconstituées, chaque plaque reconstituée étant fabriquée selon les sous-étapes suivantes dans l'ordre suivant :
∘ A1) les boîtiers électroniques sont posés sur une première peau collante côté billes,
∘ B1) moulage des boîtiers électroniques dans la résine et polymérisation de la résine, pour obtenir la plaque intermédiaire,
o C1) amincissement de la plaque intermédiaire sur la face de la plaque intermédiaire opposée aux billes,
∘ D1) retrait de la première peau collante et pose de la plaque intermédiaire sur une deuxième peau collante, côté opposé aux billes,
∘ E1) amincissement de la plaque intermédiaire sur la face côté billes,
∘ F1) formation d'une couche de redistribution côté billes,
∘ G1) retrait de la deuxième peau collante pour obtenir une plaque reconstituée d'épaisseur inférieure à l'épaisseur d'origine des boîtiers électroniques,

- plusieurs plaques reconstituées ayant été obtenues à l'issue des sous-étapes précédentes, empilement des plaques reconstituées,
- découpe des plaques reconstituées empilées pour obtenir des modules 3D.

Abstract translation: 本发明涉及的三维电子模块的大容量的制造方法，每个3D电子模块，其包括至少两个控制单元轴承的堆叠，结转表面，在该温度和工作频率进行测试。 它包括： - 使重组板的步骤中，每个板被按照以下顺序的下列子步骤重建制造：∘A1）的电子单元被放置在第一侧上的皮肤粘性珠，∘B1）成型 控制单元在所述树脂和在面板相对的中间的到珠子上，∘D1）去除所述第一粘合剂的皮肤和安装板固化该树脂，以获得中间板，邻C1）变薄中间板的 中间上的相反侧的第二粘皮到珠子上，∘E1）上的前侧轴承，∘F1）形成再分布层侧珠，∘G1）中间板变薄去除第二粘性皮肤以获得 厚度小于电子盒原始厚度的重组板， - 几个重构板，具有 TY在之前的子步骤的结束时获得，堆叠板重构， - 堆叠以获得重建的3D模块板的切削加工。