公开(公告)号：PT100693A

公开(公告)日：1994-05-31

申请号：PT10069392

申请日：1992-07-15

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06F7/00

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

公开(公告)号：ES2040660A2

公开(公告)日：1993-10-16

申请号：ES9201485

申请日：1992-07-16

Applicant: KOREA TELECOMMUNICATION

Inventor： IL SONG HAN

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06G7/02

Abstract: MULTIPLICADOR ANALOGICO CON MOSFETS. PRESENTA MEDIOS LINEALES DE MOSFET DE RESISTIVIDAD VARIABLE PARA HACER VARIAR LINEALMENTE LA INTENSIDAD "I" DE SALIDA EN FUNCION DE UNA TENSION SIMETRICA DE ENTRADA PROCEDENTE DE FUENTES "V2" Y "-V2" DE TENSION Y UNA TENSION DE ENTRADA PROCEDENTE DE UNA FUENTE "V1" DE TENSION DE ENTRADA ASOCIADA OPERATIVAMENTE CON LA TENSION SIMETRICA DE ENTRADA PROCEDENTE DE LAS FUENTES "V2" Y "-V2" DE TENSION, TENIENDO LOS MEDIOS LINEALES DE MOSFET DE RESISTIVIDAD VARIABLE UN NODO "A" PARA PRODUCIR A SU TRAVES LA INTENSIDAD "I" DE SALIDA VARIADA. LA UNIDAD AMPLIFICADORA OPERACIONAL INCLUYE ADEMAS UN ELEMENTO "Z" DE REALIMENTACION CONECTADO ENTRE EL TERMINAL DE ENTRADA DE INVERSION Y EL TERMINAL DE SALIDA DEL AMPLIFICADOR OPERACIONAL "U", PRODUCIENDO EL TERMINAL DE SALIDA UNA TENSION "VO". APLICABLE, PARTICULARMENTE, PARA OBTENER HIBRIDOS ANALOGICO-DIGITALES DE UNA SINAPSIS NEURAL ARTIFICIAL.

公开(公告)号：GR920100488A

公开(公告)日：1993-07-30

申请号：GR92100488

申请日：1992-11-05

Applicant: KOREA TELECOMMUNICATION

Inventor： CHONG RAK LEE ,  YONG KYU PARK

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90 ,  G10L5/02

公开(公告)号：SE9203230L

公开(公告)日：1993-05-07

申请号：SE9203230

申请日：1992-11-02

Applicant: KOREA TELECOMMUNICATION

Inventor： LEE C R ,  PARK Y K

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90

公开(公告)号：FR2683367A1

公开(公告)日：1993-05-07

申请号：FR9213415

申请日：1992-11-06

Applicant: KOREA TELECOMMUNICATION

Inventor： RAK LEE CHONG ,  KYU PARK YONG

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90

公开(公告)号：DK81992A

公开(公告)日：1993-05-02

申请号：DK81992

申请日：1992-06-22

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16 ,  G06G7/16

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

公开(公告)号：GB2230383B

公开(公告)日：1993-01-20

申请号：GB9006850

申请日：1990-03-27

Applicant: ELECT & TELECOMM RESEARCH INST ,  KOREA TELECOMMUNICATION

Inventor： KIM SANG-BAE

IPC: H01S5/00 ,  H01S5/227 ,  H01S5/30

Abstract: A method for manufacturing a buried heterostructure laser diode comprising an active layer and a clad layer which are formed as a reverse mesa on a substrate, current blocking layers and an insulation layer deposited on the top of the blocking layers, and an electrode formed on the top thereof comprising: a first step for forming a SiO2 stripe mask on the clad layer after a first liquid phase epitaxial growth of the active layer and the clad layer on the substrate, a second step for etching the clad layer under the SiO2 stripe mask using an etchant to form a reverse mesa structure, a third step for selectively etching the clad layer using an etchant such as a family of hydrochloric acid and then for making the active layer protrude, and a fourth step for naturally melthig back the protruded porting of the active layer surface during the second epitaxial growth process is provided.

公开(公告)号：SE9203230D0

公开(公告)日：1992-11-02

申请号：SE9203230

申请日：1992-11-02

Applicant: KOREA TELECOMMUNICATION

Inventor： LEE C R

IPC: G10L13/04 ,  G10L13/06 ,  G10L19/00 ,  G10L21/04 ,  G10L25/90

公开(公告)号：DE4010889C2

公开(公告)日：1992-09-03

申请号：DE4010889

申请日：1990-04-04

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, DAEJEON, KR ,  KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR

Inventor： SANG-BAE, KIM, DAEJEON, KR

IPC: H01S5/00 ,  H01S5/227 ,  H01S5/30

Abstract: A method for manufacturing a buried heterostructure laser diode comprising an active layer and a clad layer which are formed as a reverse mesa on a substrate, current blocking layers and an insulation layer deposited on the top of the blocking layers, and an electrode formed on the top thereof comprising: a first step for forming a SiO2 stripe mask on the clad layer after a first liquid phase epitaxial growth of the active layer and the clad layer on the substrate, a second step for etching the clad layer under the SiO2 stripe mask using an etchant to form a reverse mesa structure, a third step for selectively etching the clad layer using an etchant such as a family of hydrochloric acid and then for making the active layer protrude, and a fourth step for naturally melthig back the protruded porting of the active layer surface during the second epitaxial growth process is provided.

公开(公告)号：GB9213382D0

公开(公告)日：1992-08-05

申请号：GB9213382

申请日：1992-06-24

Applicant: KOREA TELECOMMUNICATION

IPC: G06G7/163 ,  G06N3/063 ,  H03F3/16

Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.