Abstract:
The invention provides circuitry integrated into a silicon chip that measures aspects of an RF signal on a transmission line in order to provide data that is ultimately used by an antenna tuner circuit to substantially match the impedance of the antenna with that of the transmission line providing the RF frequency to be transmitted.
Abstract:
A Reference Signal Received Power (RSRP) value is produced from a received Orthogonal Frequency Division Multiplexed (OFDM) signal that comprises a plurality of reference symbols located at known sub-carrier frequencies and times within the received OFDM signal. RSRP value production involves, for each hypothesized error state selected from a plurality of different hypothesized error states, ascertaining a corresponding hypothesized RSRP value, and then using the hypothesized RSRP values as a basis for determining a value for use as the produced RSRP value (e.g., by selecting a maximum one of the hypothesized RSRP values as the produced RSRP value). In this technology, each of the hypothesized error states is a hypothesized frequency error paired with a hypothesized timing error and the corresponding hypothesized RSRP value is produced by adjusting one or more measured channel estimates as a function of the hypothesized error state.
Abstract:
The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).
Abstract:
The present subject matter discloses a system and a method for processing of channel coefficients of networks. In one embodiment, the method includes ascertaining at least one probable synchronization position of a received sequence and projecting, by oblique projection, at least one given noise basis vector spanning a given noise space onto the null space, so as to determine a channel impulse response at the at least one probable synchronization position. Based on a criterion related to the channel impulse response, a synchronization point for the received sequence is identified from the at least one probable synchronization position. The method also includes determining the noise contribution at the synchronization point and determining the noise coefficient of the at least one given noise basis vector based on the noise contribution so as to recover a signal substantially similar to the originally transmitted signal.
Abstract:
The present subject matter discloses a system and a method for estimating a frequency offset in communication devices. In one embodiment, the method of estimating a frequency offset in a communication device comprises generating a reconstructed signal based at least in part on a channel impulse response (CIR) corresponding to a received signal. Further, a normalization matrix is determined for the reconstructed signal. Thereafter, based at least in part on the normalization matrix and the reconstructed signal, the frequency offset is estimated such that the frequency offset corresponds to a maximum normalized-correlation between the reconstructed signal and the received signal.
Abstract:
The invention concerns a system for delivering a voltage to at least one power domain (2.11-2. nz) comprising at least one component, each power domain functioning according to at least two operating points, each operating point defining a required supply voltage, the required supply voltages of the operating points of a given power domain being distinct in pairs. The system comprises at least a first and a second power supply units (1.10-1.n0), each supply unit being adapted to deliver a controllable supply voltage and the at least one power domain comprises at least one first power domain (2.1 x; 2.2y; 2.nz), which is arranged to be alternatively connected to the first or to the second power supply unit. The system further comprises a control unit (5) arranged to select, among the first and second power supply units, a current power supply unit to be connected to the first power domain, the current power supply unit being selected based on a current operating point of the first power domain, the control unit being further arranged to control the controllable supply voltage delivered by the current power supply unit to deliver the required voltage level associated with the current operating point of the first power domain.
Abstract:
A UE side Broadcast/Multicast Control (BMC) protocol layer determines those Cell Broadcast Service (CBS) messages (and their repetitions) which the UE shall read or ignore in a succeeding CBS schedule period, based on the CBS Schedule Message contents (Message Description Type and New Message Bitmap) received in a current CBS schedule period, the CBS messages already stored in the BMC, and the CBS messages to be received. In this manner, the UE may ignore CBS messages it has already received, without knowledge of the CBS message serial numbers, and thus conserve resources such as battery power.
Abstract:
A multi-mode, dynamic, DC-DC converter supplies a dynamically varying voltage, as required, from a battery to an RF power amplifier (PA). In envelope tracking mode, a fast DC-DC converter generates a dynamic voltage that varies based on the amplitude envelope of an RF signal, and regulates the voltage at the PA. A slow DC-DC converter generates a steady voltage and regulates the voltage across a link capacitor. The fast and slow converters are in parallel from the view of the PA, and the link capacitor is between the fast converter and the PA. Because different nodes are regulated, no current sharing is possible between the converters. The link capacitor boosts the dynamic voltage level, allowing a maximum dynamic voltage at the load to exceed the battery voltage. In power level tracking mode, the fast converter is disabled and the link capacitor is configured to be in parallel with the load. The slow converter directly regulates the PA, and the link capacitor is in parallel with (added to) an output capacitor. Multiple wireless network standards may be supported, allowing for the sharing of RF circuits.
Abstract:
A method is disclosed of indicating a suitable pose for a camera for obtaining a stereoscopic image, with the camera comprising an imaging sensor. The method comprises obtaining and storing a first image of a scene using the imaging sensor when the camera is in a first pose; moving the camera to a second pose; and obtaining a second image of the scene when the camera is in the second pose. One or more disparity vectors are determined, each disparity vector being determined between a feature identified within the first image and a corresponding feature identified in the second image. On the basis of the one or more disparity vectors, a determination is made of whether the second image of the scene is suitable for use, together with the first image, as a stereoscopic image pair.
Abstract:
The frequency response of a digital filter, such as a pre-emphasis filter in a signal transmitter having a phase-locked loop, is adjusted using interpolation of the filter coefficients, enabling sets of filter coefficients to be pre-computed or generated as needed in the transmitter. The phase error behavior of the digital filter can be significantly improved.