公开(公告)号：JPS6167154A

公开(公告)日：1986-04-07

申请号：JP18889184

申请日：1984-09-11

Applicant: Fujitsu Ltd

Inventor： TAKEMAE YOSHIHIRO

IPC: G11C11/401 ,  G06F9/32 ,  G06F12/02 ,  G06F12/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

CPC classification number: G11C7/1036 ,  G11C7/10 ,  G11C7/22 ,  G11C8/04 ,  G11C8/10

Abstract: PURPOSE: To simplify processing procedures of a device by accessing automatically and continuously data in plural addresses by one address input to read or write data of continuous instruction codes in a high speed.
CONSTITUTION: The memory of a semiconductor storage device is divided to memory chips 3 and 4, and word addresses A
8 WA
15 are inputted to decoders 5 and 6 through address increment circuits 7 and 8. A column decoder 9 is connected to chips 3 and 4 through input/output gate circuits 10 and 11 respectively, and word bits A
0 WA
7 are inputted to the decoder 9, and a shift register 12 is connected to circuits 10 and 11. Data in plural addresses are accessed automatically and continuously by one address input to read or write of data of continuous instruction codes from or onto chips 3 and 4 at a high speed, and processing procedures of the storage device are simplified.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过一个地址输入自动连续地访问多个地址的数据，以便高速读取或写入连续指令代码的数据，简化了设备的处理步骤。 构成：半导体存储装置的存储器分为存储芯片3和4，字地址A8-A15通过地址增加电路7和8被输入到解码器5和6.列解码器9连接到芯片3和4 分别通过输入/输出门电路10和11，并将字位A0-A7输入到解码器9，并且移位寄存器12连接到电路10和11.多个地址中的数据被一个地址输入自动连续地访问 以高速度从芯片3和芯片4读取或写入连续指令代码的数据，简化了存储装置的处理过程。

公开(公告)号：JPS60211692A

公开(公告)日：1985-10-24

申请号：JP6768784

申请日：1984-04-06

Applicant: Hitachi Ltd

Inventor： TANIMURA NOBUROU

IPC: G11C11/401 ,  G11C7/10 ,  G11C8/04 ,  G11C11/34

CPC classification number: G11C8/04 ,  G11C7/1036

Abstract: PURPOSE: To simplify a memory reading action in a certain order for refreshing by performing a reading action through an address counter and by refreshing it automatically.
CONSTITUTION: A counter for forming and outputting an adress signal after it is activated by an external timing signal is built in an automatic refresh circuit RFE. The address and a specified address from a shift register SR accomplish reading of a memory array M-ARY for refreshing in a certain order without use of microprocessor, etc.
COPYRIGHT: (C)1985,JPO&Japio

Abstract translation: 目的：通过执行地址计数器的读取操作并自动刷新，以一定顺序简化内存读取操作以进行刷新。 构成：在外部定时信号激活之后，用于形成和输出地址信号的计数器被内置在自动刷新电路RFE中。 来自移位寄存器SR的地址和指定的地址完成对存储器阵列M-ARY的读取，以便以不需要微处理器等的特定顺序进行刷新。

公开(公告)号：EP3243137A1

公开(公告)日：2017-11-15

申请号：EP16735388.7

申请日：2016-01-07

Applicant: Micron Technology, Inc.

Inventor： WHEELER, Kyle B. ,  MURPHY, Richard C. ,  MANNING, Troy A. ,  KLEIN, Dean A.

IPC: G06F12/02 ,  G06F9/30 ,  G11C7/06

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：EP2771885A1

公开(公告)日：2014-09-03

申请号：EP11874746.8

申请日：2011-10-27

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： GOLAB, Wojciech ,  PICKETT, Matthew, D. ,  KARP, Alan, H.

IPC: G11C19/00 ,  G06F12/00

CPC classification number: G11C7/1036 ,  G06F5/00 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/544 ,  G06F15/7821 ,  G06F2209/521 ,  G11C19/188 ,  G11C19/287

Abstract: A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset.

Abstract translation: 支持原子操作的可移动存储器在原子操作期间采用内置的移位能力来将数据的连续子集从存储器中的第一位置移动到第二位置。 可移动存储器包括用于存储数据的存储器。 内存具有内置的移动功能。 可移动存储器还包括在存储器上定义以在连续子集上操作的原子原语。

公开(公告)号：EP2446439B1

公开(公告)日：2013-05-15

申请号：EP10727608.1

申请日：2010-06-15

Applicant: SanDisk Technologies, Inc.

Inventor： CHIBVONGODZE, Hardwell ,  SAKAI, Manabu ,  KAMEI, Teruhiko

IPC: G11C7/10 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

公开(公告)号：EP1543523B1

公开(公告)日：2006-09-06

申请号：EP03754648.8

申请日：2003-09-17

Applicant: SanDisk Corporation

Inventor： CERNEA, Raul-Adrian

IPC: G11C7/10 ,  G11C19/28

CPC classification number: G11C19/00 ,  G11C7/1036 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.

公开(公告)号：EP1681680A3

公开(公告)日：2006-08-02

申请号：EP05077828.1

申请日：2002-09-17

Applicant: SanDisk Corporation

Inventor： Cernea, Paul Adrian

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables in parallel different selecting circuits in sequence. That particular selecting circuits that have been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuits will send the stored information through to the output buffers for output from the integrated circuit, and while in a programming mode, the selected selecting circuits will receive data from input buffers. This data will be written into memory cells.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 存储单元可以是多状态存储器单元。 有一个移位寄存器链，具有数组列的阶段。 选通脉冲通过该移位寄存器移位。 每个时钟的选通点依次并入不同的选择电路。 然后由选通启用的特定选择电路将执行一定的功能。 在读取模式中，所选择的选择电路将存储的信息发送到输出缓冲器以从集成电路输出，而在编程模式中，所选择的选择电路将从输入缓冲器接收数据。 该数据将被写入存储单元。

公开(公告)号：EP1681680A2

公开(公告)日：2006-07-19

申请号：EP05077828.1

申请日：2002-09-17

Applicant: SanDisk Corporation

Inventor： Cernea, Paul Adrian

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit, and while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

Abstract translation: 用于存储器单元阵列的列的选择电路用于保持读取数据或写入存储器单元的数据。 存储器单元可以是多态存储器单元。 有一个移位寄存器链，有一个列阵列的阶段。 选通脉冲通过该移位寄存器进行移位。 选通信号按每个时钟指向，并依次启用不同的选择电路。 已经由选通启用的特定选择电路将执行特定功能。 在读取模式下，选定的选择电路将存储的信息发送到输出缓冲器以从集成电路输出，并且在编程模式下，选定的选择电路将从输入缓冲器接收数据。 这些数据将写入存储单元。

公开(公告)号：EP1630814A1

公开(公告)日：2006-03-01

申请号：EP05358010.6

申请日：2005-08-23

Applicant: STMicroelectronics SA

Inventor： La Rosa, Francesco ,  Giovinazzi, Thierry

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/1036

Abstract: L'invention concerne un procédé de lecture de cellules mémoire (CELi,j,k) au moyen d'amplificateurs de lecture (SAi), les cellules mémoire étant reliées à des lignes de bit (BLi,j), la lecture de chaque cellule mémoire comprenant une phase de précharge de la ligne de bit à laquelle la cellule mémoire est reliée et une phase de lecture proprement dite de la cellule mémoire. Selon l'invention, chaque amplificateur de lecture (SAi) est utilisé pour précharger au moins deux lignes de bit, puis pour lire une cellule mémoire et une seule dans l'une des lignes de bit préchargées. Application notamment aux mémoires série, pour la précharge anticipée de lignes de bit ayant la même adresse partielle, pendant la réception d'une adresse de lecture.

Abstract translation: 该方法包括预充电两个位线（BLi上，j）至所连接的存储器单元（侧立，J，K），通过读出放大器（SAI）。 在一个预充电位线只有一个存储单元读取一个放大器的帮助。 列译码器，用于在预充电阶段将每个读出放大器与位线，以及用于读出相位期间每个放大器连接到仅一个位线。 因此独立claimsoft包括用于顺序存取存储器，包括存储单元。

公开(公告)号：EP0961435A3

公开(公告)日：2003-09-17

申请号：EP99108473.2

申请日：1999-04-30

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Cole, Steven R.

IPC: H04J3/16 ,  H04Q11/04

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/1078 ,  H04J3/0626 ,  H04J3/1641

Abstract: A memory buffer apparatus (29) includes an extended shift register (32) and a memory (30). The extended shift register (32) shifts a plurality of serial bits to produce a multi-bit data word. The multi-bit data word has a predetermined length based on a delay interval that is a multiple of a serial bit period. The memory (30) stores the bit-slice of the multi-bit data word. The bit-slice has a length less than that of the multi-bit data word. An extended output shift register (34) can also be included in the apparatus (29). The extended output shift register (34) has a length greater than the stored bit-slice, and performs a parallel-to-serial conversion of the bit-slice output from the memory (30).