公开(公告)号：US20230403853A1

公开(公告)日：2023-12-14

申请号：US18043080

申请日：2022-02-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H10B43/27 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H01L29/0847 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/78696

Abstract: An NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus including the NOR-type memory device. The NOR-type memory device includes: a gate stack including a gate conductor layer and a memory functional layer; and a first semiconductor layer and a second semiconductor layer that surround a periphery of the gate stack. The first and second semiconductor layers are respectively located at different heights with respect to the substrate. The memory functional layer is located between the gate conductor layer and each of the first and second semiconductor layers. Each of the first and second semiconductor layers includes a first source/drain region, a channel region, and a second source/drain region that are disposed in sequence in a vertical direction. A memory cell is defined at an intersection of the gate stack and each of the first and second semiconductor layers.

公开(公告)号：US11842931B2

公开(公告)日：2023-12-12

申请号：US17037350

申请日：2020-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L21/8234 ,  H01L21/761 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/26533 ,  H01L21/761 ,  H01L21/762 ,  H01L21/76208 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823821

Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

公开(公告)号：US20230397504A1

公开(公告)日：2023-12-07

申请号：US18249805

申请日：2021-05-17

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guozhong Xing ,  Di Wang ,  Ming Liu

IPC: H10N52/00 ,  H10N52/85 ,  H10N59/00 ,  G06N3/063

CPC classification number: H10N52/101 ,  H10N52/85 ,  H10N59/00 ,  G06N3/063

Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

公开(公告)号：US20230394291A1

公开(公告)日：2023-12-07

申请号：US18034365

申请日：2021-07-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACANDEMY OF SCIENCES

Inventor： Guozhong XING ,  Di Wang ,  Huai LIN ,  Long LIU ,  Ming LIU

IPC: G06N3/063 ,  H01F10/32 ,  H10N50/85 ,  H10N52/00

CPC classification number: G06N3/063 ,  H01F10/3286 ,  H10N50/85 ,  H10N52/00 ,  G11C11/161

Abstract: A neuron device including: an antiferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to a spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer formed on two sides of the free layer and having opposite magnetization directions; and a reference layer formed on the tunneling layer; wherein the free layer, the tunneling layer and the reference layer constitute a magnetic tunnel junction, and the magnetic tunnel junction is configured to read neuronal signals. Also provided is a method for preparing a neuron device based on a spin orbit torque.

公开(公告)号：US20230392982A1

公开(公告)日：2023-12-07

申请号：US18034050

申请日：2020-11-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jing LI ,  Huijuan MA ,  Minxia DING ,  Zhipeng WU ,  Dan WANG

IPC: G01J1/44 ,  G01J1/02

CPC classification number: G01J1/44 ,  G01J1/0252 ,  G01J1/0219 ,  G01J2001/448 ,  G01J2001/444

Abstract: A photoelectric detection device, including: a vacuum sealed housing, wherein the vacuum sealed housing includes a mounting interface for mounting the photodetector array so as to form a sealed space; the photodetector array has a detection surface facing an outside of the vacuum sealed housing and configured to receive multi-channel measurement optical signals; a photoelectric conversion and synchronous acquisition circuit and a high speed transmission circuit board are placed in the vacuum sealed housing, and the photodetector array is connected to the photoelectric conversion and synchronous acquisition circuit through a signal pin of the photodetector array; the photoelectric conversion and synchronous acquisition circuit is configured to synchronously convert the multi-channel measurement optical signals obtained by the photodetector array into multi-channel digital signals; and the high speed transmission circuit board is configured to perform a serial encoding processing on the converted multi-channel digital signals.

公开(公告)号：US11839085B2

公开(公告)日：2023-12-05

申请号：US17423082

申请日：2019-11-04

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Zhaozhao Hou ,  Tianchun Ye ,  Chaolei Li

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H10B51/30

Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.

公开(公告)号：US20230380133A1

公开(公告)日：2023-11-23

申请号：US18318794

申请日：2023-05-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: Disclosed are a memory device, a method of manufacturing the same, and an electronic apparatus. The memory device includes: first to fourth connection line layers sequentially disposed in a vertical direction relative to a substrate. The first connection line layer includes a plurality of first conductive lines extending parallel in a first direction. One of the second and third connection line layers includes a plurality of conductive lines extending parallel in a second direction intersecting the first direction. The fourth connection line layer includes a plurality of fourth conductive lines extending parallel in a third direction. A memory cell is provided at an intersection of conductive lines. Each memory cell includes first to third transistors stacked in the vertical direction. A fifth connection line layer is provided above the memory cell, and includes a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction.

公开(公告)号：US11810902B2

公开(公告)日：2023-11-07

申请号：US17548289

申请日：2021-12-10

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/535 ,  H01L23/544 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2225/06524 ,  H01L2225/06544

Abstract: A semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a plurality of element stacks, wherein each element stack includes a plurality of stacked layers of semiconductor elements, each semiconductor element includes a gate electrode and source/drain regions on opposite sides of the gate electrode; and an interconnection structure between the plurality of element stacks. The interconnection structure includes an electrical isolation layer, and a conductive structure in the electrical isolation layer. At least one of the gate electrode and the source/drain regions of each of at least a part of the semiconductor elements is in contact with and therefore electrically connected to the conductive structure of the interconnection structure at a corresponding height in a lateral direction.

公开(公告)号：US11810823B2

公开(公告)日：2023-11-07

申请号：US17037364

申请日：2020-09-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L21/823481 ,  H01L21/26533 ,  H01L21/3081 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/7848

Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

公开(公告)号：US20230343851A1

公开(公告)日：2023-10-26

申请号：US17783624

申请日：2021-12-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Weixing HUANG ,  Huilong ZHU

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are sequentially formed on a substrate. Then, a part of the semiconductor layer is removed through etching a sidewall of the semiconductor layer to form a cavity. Afterwards, a channel layer is formed at the cavity, a sidewall of the first electrode layer, and a sidewall of the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. Then, a part of the dummy gate layer is removed through etching a sidewall of the dummy gate layer with the second channel part serving as a shield. Afterwards, the second channel part and the first channel part, which is in contact with an upper surface and a lower surface of the dummy gate layer, are removed to form a recess. The recess is formed by either the first electrode layer or the second electrode layer, the channel layer, and the dummy gate layer. The recess is filled with a dielectric material to form an isolation sidewall. The formed isolation sidewall can reduce parasitic capacitance of the semiconductor device and improve a performance of the semiconductor device.