公开(公告)号：US09865686B2

公开(公告)日：2018-01-09

申请号：US14646583

申请日：2013-08-12

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Huilong Zhu ,  Xiaolong Ma

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/306 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L21/28 ,  H01L29/267 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

公开(公告)号：US20230005937A1

公开(公告)日：2023-01-05

申请号：US17779723

申请日：2019-12-10

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Xiang Lin ,  Yanna Luo ,  Zhanfeng Liu

IPC: H01L27/11

Abstract: The method for manufacturing a three-dimensional static random-access memory, including: manufacturing a first semiconductor structure including multiple MOS transistors and a first insulating layer thereon; bonding a first material layer to the first insulating layer to form a first substrate layer; manufacturing multiple first low-temperature MOS transistors at a low temperature on the first substrate layer, and forming a second insulating layer thereon to form a second semiconductor structure; bonding a second material layer to the second insulating layer to form a second substrate layer; manufacturing multiple second low-temperature MOS transistors at a low temperature on the second substrate layer, and forming a third insulating layer thereon to form a third semiconductor structure; and forming an interconnection layer which interconnets the first semiconductor structure, the second semiconductor structure and the third semiconductor structure.

公开(公告)号：US11257933B2

公开(公告)日：2022-02-22

申请号：US17029495

申请日：2020-09-23

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Qingzhu Zhang ,  Renren Xu

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8238

Abstract: A method for manufacturing a semiconductor device is provided. A first substrate and at least one second substrate are provided. A single crystal lamination structure is formed on the first substrate. The single crystal lamination structure includes at least one hetero-material layer and at least one channel material layer that are alternately laminated, each of the at least one hetero-material layer is bonded to an adjacent one of the at least one channel material layer at a side away from the first substrate, and each of the at least one channel material layer is formed from one of the at least one second substrate. At least one layer of nanowire or nanosheet is formed from the single crystal lamination structure. A gate dielectric layer and a gate which surround each of the at least one layer of nanowire or nanosheet is formed. A semiconductor device is also provided.

公开(公告)号：US10096691B2

公开(公告)日：2018-10-09

申请号：US14812490

申请日：2015-07-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qingzhu Zhang ,  Lichuan Zhao ,  Xiongkun Yang ,  Huaxiang Yin ,  Jiang Yan ,  Junfeng Li ,  Tao Yang ,  Jinbiao Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L29/417 ,  H01L21/28

Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

公开(公告)号：US09892912B2

公开(公告)日：2018-02-13

申请号：US14688788

申请日：2015-04-16

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Zuozhen Fu ,  Xiaolong Ma ,  Dapeng Chen

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

公开(公告)号：US09391073B2

公开(公告)日：2016-07-12

申请号：US14397822

申请日：2013-08-06

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Weijia Xu ,  Qiuxia Xu ,  Huilong Zhu

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract translation: FinFET器件及其制造方法。 FinFET器件包括多个翅片，每个翅片沿基底上的第一方向延伸; 多个栅极堆叠，每个栅极叠堆叠跨越所述多个散热片并沿第二方向延伸; 多个源/漏区对，每个源极/漏极区对的各个源极/漏极区在第二方向上设置在每个栅极堆叠的相对侧上; 以及多个通道区域，每个沟道区域包括在相应的源极/漏极对的各个源极/漏极区域之间的相应鳍片的一部分，其中每个鳍片包括在第二方向的相对侧表面上的多个突起单元。

公开(公告)号：US20160071952A1

公开(公告)日：2016-03-10

申请号：US14725666

申请日：2015-05-29

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Guilei Wang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在基板上形成沿第一方向延伸的多个翅片; 在翅片上形成沿着第二方向延伸的虚拟栅极堆叠; 在第一方向上在虚拟栅极堆叠的相对侧上形成栅极间隔物; 在第一方向上在栅极间隔物的相对侧的翅片的顶部外延生长凸起的源极/漏极区域; 通过栅极间隔物作为掩模，通过凸起的源极/漏极区进行轻掺杂离子注入，以在第一方向上在栅极间隔物的相对侧的鳍中形成源极/漏极延伸区域; 去除虚拟栅极堆叠以形成栅极沟槽; 以及在栅极沟槽中形成栅叠层。

公开(公告)号：US20230326965A1

公开(公告)日：2023-10-12

申请号：US18087347

申请日：2022-12-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Anlan Chen ,  Fei Zhao ,  Xiaohong Cheng ,  Huaxiang Yin ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

公开(公告)号：US11594608B2

公开(公告)日：2023-02-28

申请号：US16561192

申请日：2019-09-05

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huaxiang Yin ,  Jiaxin Yao ,  Qingzhu Zhang ,  Zhaohao Zhang ,  Tianchun Ye

IPC: H01L29/423 ,  H01L21/225 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

公开(公告)号：US11456218B2

公开(公告)日：2022-09-27

申请号：US17004173

申请日：2020-08-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guilei Wang ,  Henry H Radamson ,  Zhenzhen Kong ,  Junjie Li ,  Jinbiao Liu ,  Junfeng Li ,  Huaxiang Yin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.