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    Method for forming gate-all-around nanowire device
    2.
    发明授权
    Method for forming gate-all-around nanowire device 有权

    公开(公告)号：US11594608B2

    公开(公告)日：2023-02-28

    申请号：US16561192

    申请日：2019-09-05

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Huaxiang Yin ,  Jiaxin Yao ,  Qingzhu Zhang ,  Zhaohao Zhang ,  Tianchun Ye

    IPC: H01L29/423 ,  H01L21/225 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

    Abstract: A gate-all-around nanowire device and a method for forming the gate-all-around nanowire device. A first fin and a dielectric layer on the first fin are formed on a substrate. The first fin includes the at least one first epitaxial layer and the at least one second epitaxial layer that are alternately stacked. The dielectric layer exposes a channel region of the first fin. A doping concentration at a lateral surface of the channel region and a doping concentration at a central region of the channel region are different from each other in the at least one second epitaxial layer. After the at least one first epitaxial layer is removed from the channel region, the at least one second epitaxial layer in the channel region serves as at least one nanowire. A gate surrounding the at least one nanowire is formed.

    Method for manufacturing P-type MOSFET
    4.
    发明授权
    Method for manufacturing P-type MOSFET 有权
    制造P型MOSFET的方法

    公开(公告)号：US09196706B2

    公开(公告)日：2015-11-24

    申请号：US14004802

    申请日：2012-12-07

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Qiuxia Xu ,  Huilong Zhu ,  Tianchun Ye ,  Huajie Zhou ,  Gaobo Xu ,  Qingqing Liang

    IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423

    CPC classification number: H01L29/66545 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3215 ,  H01L29/42364 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

    Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

    Abstract translation: 提供一种用于制造p型MOSFET的方法，包括：在包括源极/漏极区域的半导体衬底上形成MOSFET的一部分，替换栅极和栅极间隔物; 去除MOSFET的替换栅极堆叠以形成栅极开口; 在所述半导体衬底的所述暴露表面上形成界面氧化物层; 在界面氧化物层上形成高K栅介电层; 形成第一金属栅极层; 将掺杂剂离子注入第一金属栅极层; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 在高K栅极电介质层和界面氧化物层之间的下界面处通过界面反应产生电偶极子。

    Semiconductor device and manufacturing method thereof
    7.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11056580B2

    公开(公告)日：2021-07-06

    申请号：US15757601

    申请日：2015-11-23

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Tianchun Ye

    IPC: H01L21/02 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11568

    Abstract: A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.

    Method of manufacturing a semiconductor device
    8.
    发明授权
    Method of manufacturing a semiconductor device 有权

    公开(公告)号：US10483279B2

    公开(公告)日：2019-11-19

    申请号：US15753376

    申请日：2015-11-23

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Tianchun Ye

    IPC: H01L21/02 ,  H01L27/11582 ,  H01L21/306 ,  H01L21/324 ,  H01L21/28 ,  H01L29/792

    Abstract: A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.

    A METHOD FOR OPERATING A SEMICONDUCTOR MEMORY
    9.
    发明申请
    A METHOD FOR OPERATING A SEMICONDUCTOR MEMORY 审中-公开

    公开(公告)号：US20180315484A1

    公开(公告)日：2018-11-01

    申请号：US15769619

    申请日：2015-11-23

    Applicant: Institute of Microelectronics, Chinese Academy of Sciences

    Inventor： Tianchun Ye

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/08

    Abstract: A method for operating a semiconductor memory includes: randomizing a data of an operation address to obtain a random code; performing a combinational logic operation between the random code and the original data to obtain a randomized data, or performing a combinational logic operation between the randomized data and the random code to obtain a de-randomized data; saving the randomized data, or outputting the de-randomized data. According to the method for operating a semiconductor memory of the present invention, since a combinational logic or a non-iterative sequential logic is used to form a random sequence generation unit, the encoding/decoding process does not need to wait for a specific cycle, thus reducing the operation time and improving the chip performance.

    Data recovery method for flash memory
    10.
    发明授权
    Data recovery method for flash memory 有权

    公开(公告)号：US12197282B2

    公开(公告)日：2025-01-14

    申请号：US18553929

    申请日：2021-04-08

    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

    Inventor： Qianhui Li ,  Qi Wang ,  Liu Yang ,  Yiyang Jiang ,  Xiaolei Yu ,  Jing He ,  Zongliang Huo ,  Tianchun Ye

    IPC: G06F11/10 ,  G06F11/14

    Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

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