公开(公告)号：WO2008012464A2

公开(公告)日：2008-01-31

申请号：PCT/FR2007051705

申请日：2007-07-20

Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

Inventor： LA ROSA FRANCESCO

IPC: G11C16/26

CPC classification number: G11C16/22 ,  G04F10/10 ,  G11C16/0441 ,  G11C16/26

Abstract: The invention relates to an electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each comprising a selection transistor in series with a floating-gate transistor, the circuit comprising, on any one row of memory cells: a first subassembly of at least a first cell (C1), the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell (C2), the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell (7); and a fourth subassembly of at least a fourth cell (6), the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

Abstract translation: 本发明涉及一种用于时间测量的电子电荷保持电路，其被注入到一个EEPROM存储单元的阵列中，每个EEPROM存储单元包括与浮置栅极晶体管串联的选择晶体管，该电路在任何一行存储单元上包括：第一 至少第一单元（C1）的子组件，其浮栅晶体管的隧道窗口的电介质的厚度小于其它单元的电介质的厚度; 至少第二单元（C2）的第二子组件，其浮置晶体管的漏极和源极相互连接; 至少第三电池（7）的第三子组件; 以及至少第四单元（6）的第四子组件，其通道窗口被省略，四个子组件的单元的晶体管的相应浮动栅互连。

公开(公告)号：WO2008012463A2

公开(公告)日：2008-01-31

申请号：PCT/FR2007051701

申请日：2007-07-20

Applicant: ST MICROELECTRONICS SA ,  LA ROSA FRANCESCO

Inventor： LA ROSA FRANCESCO

IPC: G11C27/02

CPC classification number: G11C27/024 ,  G04F10/10 ,  G11C27/005

Abstract: The invention relates to a method of controlling an electronic charge retention circuit for time measurement, comprising at least a first capacitive element (C1), the dielectric of which has a leakage, and at least a second capacitive element (C2), the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node (F) that can be connected to an element (5) for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.

Abstract translation: 本发明涉及一种控制用于时间测量的电子电荷保持电路的方法，该方法至少包括其电介质具有泄漏的第一电容元件（C1）和至少第二电容元件（C2） 其具有比第一电容高的电容，所述两个元件具有限定浮动节点（F）的公共电极，该电极可以连接到用于测量其剩余电荷的元件（5），其中电荷保持周期被编程或初始化 通过第一元素注入或提取电荷。

公开(公告)号：WO2007057616A3

公开(公告)日：2007-08-23

申请号：PCT/FR2006051189

申请日：2006-11-17

Applicant: ST MICROELECTRONICS SA ,  RIVET BERTRAND ,  GAUTIER FREDERIC ,  PERON BENOIT

Inventor： RIVET BERTRAND ,  GAUTIER FREDERIC ,  PERON BENOIT

IPC: G09G3/28

CPC classification number: G09G5/00 ,  G09G2360/16

Abstract: The invention relates to a method and a circuit for controlling an energy recovery stage of a plasma screen comprising a resonant circuit of at least one inductive element (L) and of a capacitive element (Cs), in which the capacitive element is precharged halfway with a supply voltage (Vs) of the screen.

Abstract translation: 本发明涉及一种用于控制等离子体屏幕的能量回收阶段的方法和电路，其包括至少一个电感元件（L）和电容元件（Cs）的谐振电路，其中电容元件在中途预充电 屏幕的电源电压（Vs）。

公开(公告)号：WO2007010167A3

公开(公告)日：2007-04-05

申请号：PCT/FR2006050726

申请日：2006-07-18

Applicant: ST MICROELECTRONICS SA ,  MARGUERY PHILIPPE ,  CHESNEAU DAVID

Inventor： MARGUERY PHILIPPE ,  CHESNEAU DAVID

IPC: H04M1/725 ,  H02J7/34 ,  H02M3/158

CPC classification number: H02J7/34 ,  H02M3/1588 ,  Y02B40/90 ,  Y02B70/1466

Abstract: The invention concerns a DC/DC converter-regulator designed to connect a fuel cell (14) to a filter (17) adapted to be connected to means for electrochemical storage (11) of electric power during a charging operation of the storage means. The converter-regulator comprises means (22, 28, 30) adapted to maintain, during the charging operation, the voltage (VFC) at the terminals of the fuel cell, at a given operating voltage.

Abstract translation: 本发明涉及一种设计用于将燃料电池（14）连接到过滤器（17）的DC / DC转换器调节器，所述过滤器（17）适于在存储装置的充电操作期间连接到电力电化学存储装置（11）。 转换器调节器包括适于在充电操作期间在给定工作电压下维持燃料电池端子处的电压（VFC）的装置（22,28,30）。

公开(公告)号：WO2006054024A3

公开(公告)日：2007-02-01

申请号：PCT/FR2005050959

申请日：2005-11-17

Applicant: ST MICROELECTRONICS SA ,  HERNANDEZ CAROLINE

Inventor： HERNANDEZ CAROLINE

IPC: H01L21/68 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/78 ,  H01L25/50 ,  H01L31/18 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention concerns a method for thinning a first semiconductor wafer (1) from a first side (12), which consists in applying, on the second side of the first wafer, a second wafer (3) with an interposed photoresist layer (2).

Abstract translation: 本发明涉及一种用于从第一侧（12）减薄第一半导体晶片（1）的方法，该方法包括在第一晶片的第二侧上施加具有中间光刻胶层（2）的第二晶片（3） 。

公开(公告)号：WO2004027688A3

公开(公告)日：2004-05-13

申请号：PCT/FR0350055

申请日：2003-09-19

Applicant: ST MICROELECTRONICS SA ,  DEVEAUD VINCENT ,  LIARDET PIERRE-YVAN

Inventor： DEVEAUD VINCENT ,  LIARDET PIERRE-YVAN

IPC: H03K19/00 ,  G06F21/75 ,  G06F21/81 ,  G06K19/073 ,  H04K3/00 ,  H04L9/10 ,  G06F1/00

CPC classification number: G06F21/75 ,  G06F21/81 ,  G06K19/073

Abstract: The invention relates to a method and feed circuit for an asynchronous calculation element (1) of an integrated circuit, wherein the instantaneous power supply of the calculation element is randomly varied .

Abstract translation: 本发明涉及用于集成电路的异步计算元件（1）的方法和馈电电路，其中计算元件的瞬时电源是随机变化的。

公开(公告)号：WO0245261A3

公开(公告)日：2003-05-30

申请号：PCT/FR0103788

申请日：2001-11-29

Applicant: ST MICROELECTRONICS SA ,  MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

Inventor： MOURET MICHEL ,  SABUT MARC ,  VAN ZANTEN FRANCOIS

IPC: H03G7/06

CPC classification number: H03G7/06

Abstract: The invention concerns a controllable set of current sources (6') comprising several output terminals (Si), a first transistor (T1i') associated with each first output terminal, the current (li) on each first output terminal depending on the current passing through the first transistor, and control means (8) designed, in response to a predetermined control voltage variation (VAB), to make each first transistor (T1i') gradually conductive then gradually non-conductive, wherein the first transistors are MOS transistors, and wherein each first output terminal (Si) is associated with a current mirror formed by MOS transistors (T2i, T3i), said current mirror supplying to the first output terminal a current dependent on the current passing through the first transistor.

Abstract translation: 本发明涉及一组可控的电流源（6'），其包括多个输出端子（Si），与每个第一输出端子相关联的第一晶体管（T1i'），每个第一输出端子上的电流（li）取决于电流通过 通过第一晶体管和响应于预定控制电压变化（VAB）而设计的控制装置（8）使得每个第一晶体管（T1i'）逐渐导通，然后逐渐不导电，其中第一晶体管是MOS晶体管， 并且其中每个第一输出端子（Si）与由MOS晶体管（T2i，T3i）形成的电流镜相关联，所述电流镜向第一输出端子提供取决于通过第一晶体管的电流的电流。

公开(公告)号：WO2007083019A3

公开(公告)日：2008-01-17

申请号：PCT/FR2007000082

申请日：2007-01-17

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS ASIA ,  LEBOWSKY FRITZ ,  HUANG YONG

Inventor： LEBOWSKY FRITZ ,  HUANG YONG

IPC: H04N5/208

CPC classification number: H04N5/208

Abstract: The invention concerns a device for processing a digital image comprising at least one contour region, including sharpness processing of the contour region. The sharpness processing includes converting data of the level of pixels of the contour zone into initial main data (step 2), ranging between a minimum value, for example 0 and a main value based on the amplitude of the contour, a sharpness sub-processing performed on said initial main data so as to obtain final main data (steps 3 to 10), and converting the final main data into final data of levels (step 11).

Abstract translation: 本发明涉及一种用于处理包括至少一个轮廓区域的数字图像的装置，包括轮廓区域的锐度处理。 锐度处理包括将轮廓区域的像素级的数据转换为初始主数据（步骤2），基于轮廓的幅度在最小值（例如0）和主值之间进行测距，锐度子处理 对所述初始主数据执行以获得最终主数据（步骤3至10），并将最终主数据转换为最终数据级（步骤11）。

公开(公告)号：WO2006032823A3

公开(公告)日：2006-12-07

申请号：PCT/FR2005050772

申请日：2005-09-23

Applicant: ST MICROELECTRONICS SA ,  MARINET FABRICE

Inventor： MARINET FABRICE

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention concerns the generation of a chip identifier (2) bearing at least one integrated circuit, which consists in providing a cutout of least one conductive path (4) by cutting the chip, the position of the cutting line (3) relative to the chip conditioning the identifier.

Abstract translation: 本发明涉及产生具有至少一个集成电路的芯片标识符（2），其包括通过切割芯片来提供至少一个导电路径（4）的切口，切割线（3）相对于该切割线 芯片调理标识符。

公开(公告)号：WO2005009047A3

公开(公告)日：2005-06-02

申请号：PCT/FR2004001791

申请日：2004-07-08

Applicant: ST MICROELECTRONICS SA ,  NICOLAI JEAN

Inventor： NICOLAI JEAN

IPC: H04N7/167 ,  H04N7/52

CPC classification number: H04N7/1675 ,  H04N21/23614 ,  H04N21/23897 ,  H04N21/4348 ,  H04N21/8455

Abstract: The invention concerns a method for inserting synchronization marks (200) in a standardized stream of compressed and encrypted data, which consists in encrypting bit by bit one part at least of a stream of compressed data, by block encryption, and which consists in inserting a synchronization mark in the stream only after the number of encrypted bits reaches or exceeds the number of bits of the encryption block.

Abstract translation: 本发明涉及一种用于在压缩和加密数据的标准化流中插入同步标记（200）的方法，该方法包括至少一个压缩数据流的一个部分加密，通过块加密，并且其包括： 仅在加密位数达到或超过加密块的位数后才在流中进行同步标记。