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    METHOD FOR INSERTING SYNCHRONIZATION MARKS IN A VIDEO STREAM, COMPATIBLE WITH BLOCK ENCRYPTION
    1.
    发明申请
    METHOD FOR INSERTING SYNCHRONIZATION MARKS IN A VIDEO STREAM, COMPATIBLE WITH BLOCK ENCRYPTION 审中-公开
    在视频流中插入同步标记的方法，与块加密兼容

    公开(公告)号：WO2005009047A3

    公开(公告)日：2005-06-02

    申请号：PCT/FR2004001791

    申请日：2004-07-08

    Applicant: ST MICROELECTRONICS SA ,  NICOLAI JEAN

    Inventor： NICOLAI JEAN

    IPC: H04N7/167 ,  H04N7/52

    CPC classification number: H04N7/1675 ,  H04N21/23614 ,  H04N21/23897 ,  H04N21/4348 ,  H04N21/8455

    Abstract: The invention concerns a method for inserting synchronization marks (200) in a standardized stream of compressed and encrypted data, which consists in encrypting bit by bit one part at least of a stream of compressed data, by block encryption, and which consists in inserting a synchronization mark in the stream only after the number of encrypted bits reaches or exceeds the number of bits of the encryption block.

    Abstract translation: 本发明涉及一种用于在压缩和加密数据的标准化流中插入同步标记（200）的方法，该方法包括至少一个压缩数据流的一个部分加密，通过块加密，并且其包括： 仅在加密位数达到或超过加密块的位数后才在流中进行同步标记。

    Integrated circuit equipped with programmable internal clock
    3.
    发明专利
    Integrated circuit equipped with programmable internal clock 审中-公开
    集成电路配有可编程内部时钟

    公开(公告)号：JP2003084859A

    公开(公告)日：2003-03-19

    申请号：JP2002161409

    申请日：2002-06-03

    Applicant: St Microelectronics Sa ,  エステーミクロエレクトロニクス ソシエテ アノニム

    Inventor： NICOLAI JEAN

    IPC: G06F1/04 ,  G06F1/08 ,  H03K3/0231

    CPC classification number: G06F1/08 ,  H03K3/0231

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit equipped with an internal clock having no such defect that an oscillating frequency fluctuates in dependence on a power supply voltage of a circuit or variation in manufacturing. SOLUTION: In this integrated circuit, a processor (CPU) and an oscillator (OSC) are integrated in the same substrate, and a data resistor (R1) which can be loaded by the processor is provided. The oscillator functions as a clock for the processor, and is a relaxation oscillator equipped with a capacitor (C) and a current source for charge and discharge of the capacitor. The data resistor controls frequency adjustment of the relaxation oscillator by controlling the value of the charge and discharge current of the capacitor, and is loaded by the processor from an electrically programmable and nonvolatile memory (M1) provided in the same substrate of the integrated circuit while storing frequency correction data.

    Abstract translation: 要解决的问题：提供一种配备有内部时钟的集成电路，该内部时钟没有这样的缺陷，即振荡频率根据电路的电源电压或制造变化而波动。 解决方案：在该集成电路中，处理器（CPU）和振荡器（OSC）集成在同一衬底中，并且提供可由处理器加载的数据电阻器（R1）。 振荡器用作处理器的时钟，并且是配备有电容器（C）的弛豫振荡器和用于电容器的充电和放电的电流源。 数据电阻器通过控制电容器的充电和放电电流的值来控制张弛振荡器的频率调节，并且由处理器从设置在集成电路的同一衬底中的电可编程和非易失性存储器（M1）加载， 存储频率校正数据。

    4.
    发明专利
    未知

    公开(公告)号：DE602005002691D1

    公开(公告)日：2007-11-15

    申请号：DE602005002691

    申请日：2005-07-07

    Applicant: ST MICROELECTRONICS SA

    Inventor： NICOLAI JEAN ,  MARTINEZ ALBERT

    IPC: G06F13/28 ,  G06F12/10 ,  G06F12/1081

    Abstract: The process involves applying a physical address to an address bus, and delivering a signal having a value to a direct memory access controller (6). A signal with a value, different from the former, is delivered to the bus entities via drive lines. When the signal with the former value is delivered, the controller selects a register from source and destination registers and stores in it the address read on the bus. The physical address is translated from a virtual address by a memory management unit (MMU) (3). An independent claim is also included for a system on chip.

    7.
    发明专利
    未知

    公开(公告)号：DE602005006894D1

    公开(公告)日：2008-07-03

    申请号：DE602005006894

    申请日：2005-06-13

    Applicant: ST MICROELECTRONICS SA

    Inventor： FRONTE DANIELE ,  NICOLAI JEAN ,  MARTINEZ ALBERT

    IPC: G06F13/28

    Abstract: The virtual address is divided into two bit fields. Address words (A1, A2) of N bits are created for respective bit fields. The bits include distinct prefixes (pref1, pref2) having a given value associated to the fields and coded with a number strictly greater than one. A direct memory access (DMA) controller programming is executed using storing instructions having respective address words created for the respective fields. Independent claims are also included for the following: (A) a computer program having a DMA controller programming from a virtual address among a source virtual address; (B) a system-on-chip having a CPU.

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