Abstract:
A switching system using an asynchronous packet switching technique. The packets may contain voice, data or video signals. The switching speed is increased owing to the processor (SPC) analyzing only some spacial packets and that it is located out of the transmission path of the packets. It may thus process these special packets at a lower speed than the transmission speed. This system also includes a header correction circuit (HC) which improves the quality of the transmission.
Abstract:
Packet switching network with first (DN) and second (RN) cascaded parts including first and second switching modules respectively. In the second switching modules the path selection is controlled by routing information contained in the packets. In the first switching modules this selection is performed without using routing information only for a path set up packet, whilst for the following packets use is made of routing information on the route followed by the path set up packet. Each module decides to multiplex an input stream on an output only when a calculated traffic load is smaller than a limit value. This load is calculated from traffic load parameters contained in the path set up packet.
Abstract:
In this system each payphone station (PP) is provided with an alphanumerical keyboard for typing messages. These text code messages are transmitted to a common transcoder (TR) wherein they are transcoded to a second code which is e.g. a facsimile code or a telex code. The second code messages are then transmitted either to a selected facsimile station (FS) or to a telex station (TS) for being printed out.
Abstract:
An image signal (V1) is transform coded in a Discrete Cosine Transform Coder (DCT) and the output coefficients thus provided are encoded in a zonal encoder (QZ). The output of QZ is inversely coded (IQZ) and substrated from the coefficients of the DCT. The resulting error is encoded in an entropy encoder. Both the zonal coder and the entropy encoder have quality inputs (TZQ, TEQ) controlling the compression factor, and have their outputs combined in a single compressed data stream (TXD3).
Abstract:
To supervise a telephone subscriber line (v'2, v'1) and provide it with adjustable AC and DC termination impedances from the exchange (v1, v2), these are supplied by an impedance synthesis multiple loop split into separate DC and AC loop parts by filters at the output of a sense amplifier in the common loop part and fed (e) through a Herter bridge. The amplifier AC output has however to be limited to avoid saturation by a larger DC signal. It now includes a Miller effect integrator output stage (A2) with a low pass frequency response supplying the DC loop and also feeding back an input stage (A1) so that the latter exhibits a high pass frequency response with a DC free output to drive the AC loop and the consequent ability to supply a larger AC output.
Abstract:
The transducer includes a differential input stage (DIS) having an output (03) controlling the gate of an output transistor (P3) whose main current path is connected between the poles of a DC supply source in series with three resistances (R1/3). The junction of the first (R1) and second (R2) resistances is connected to one input (I2) of the differential stage and the junction of the second (R2) and third (R3) resistances constitutes an output (02) of the transducer having another output constituted by the junction of the transistor (P3) and the first resistance (R1).
Abstract:
The measurement equipment (SMC) is used in a telecommunication switching system to check if the cell rate of each of a plurality of individual cell streams multiplexed in a same link remains within the limits on the basis of which its multiplexing was allowed. To this end the equipment checks at the end of each measurement interval (MTI) and for a plurality of cell rates [(M-S)/A, (M-S/2)/A,...] if the expected probabilities to exceed these cell rates are exceeded or not. In the positive the cell rate is limited by dropping cells. Thus an expected complementary (with respect to 1) cumulative probability distribution function of the cell rate is approximated by a staircase-shaped function.
Abstract:
Communication switching element (SE) with a plurality of input receiver circuits (RC01/16), a plurality of output transmitter circuits (TC01/17), and a plurality of control circuits (CMC01/08) each with a data write bus (DB01/08), with a plurality of data buffers (DB0101/1601; DB0108/1608) coupling the input circuits to the data bus, and with a plurality of RAMs (RAM0101/1701; RAM0108/1708) each with an input individually connected to the data write bus and with an output individually connected to a respective one of the output circuits.
Abstract:
The subjects of the present invention are a bistate device (ST), a current source (BS), a bistable device (FF) and an input circuit (IC) which are all associated to constitute a signal comparator. The bistate device (ST) is a Schmitt trigger which includes current control devices (N17, P13; N18, P14) to provide a current for counterbalancing the deviation of the construction parameters of the transistors so that the operation characteristics of this device remain identical from one process to another. The current source (BS) uses a current mirror configuration and is controlled via a branch coupled between the voltage supply terminals (VDD; VSS), two (N2, N3) of the four (N1 to N4) series connected transistors forming part of this branch have a greater Width-by-Length W/L channel parameter so that identical current sources (BS) may be produced on a large scale because the current (I5; II) supplied by the latter is then independent of the threshold voltages of the constituent transistors. The bistable device (FF) is a fliflop circuit which has differential commoned input and output terminals (T1; T2) and is used to associate the input circuit (IC) having a differential analog output and the bistate device (ST) having a differential digital input. This bistate device has its input/output terminals shunted by a MOS transistor (N14) at every high clock signal (CLK) by which the common voltage on its terminals is then half way between the supply voltages so that, when the state changes, these voltages have only to vary by half instead of the full voltage difference. This allows a faster switching of the bistable device. The input circuit (IC) is an high frequency differential input (I1; I2)/double ended output (T1; T2) circuit.
Abstract:
A fast hammering printer head including an electromagnet (25 to 37) and a hammering element (45 to 48, 50) fixed to a leafspring (38 to 44, 49) and constituted by a plate (46) made of magnetically attractable material from the centre of which extends a stem (47) which ends with a printing head (50). The plate and the stem protrude from opposite sides of the leafspring, a nut (48) being engaged on this stem so as to press the plate against the leafspring to which it is adjacent. The invention also concerns a method to print on moving documents, e.g. envelops of letters, using such a hammering printer head. The method consists in attracting the plate by a first force generated by the electromagnet and thereby bending the leafspring, in releasing this plate by suppressing the first force so as to allow the displacement of the hammering element by the bent leafspring until the impact on the document, and in generating a second force by the electromagnet prior to the occurrence of this impact.