CURRENT CONTROL CIRCUIT
    3.
    发明申请
    CURRENT CONTROL CIRCUIT 审中-公开
    电流控制电路

    公开(公告)号:WO1991009440A1

    公开(公告)日:1991-06-27

    申请号:PCT/EP1989001609

    申请日:1989-12-19

    CPC classification number: G06F13/4081 H02H9/004

    Abstract: A current control circuit for a circuit board carrying a parallel circuit comprising an input capacitor (Cb) shunted by an electronic circuit (IC) constituted by CMOS devices which do not dissipate power as long as no clock signal (CK) is applied to them. This control circuit limits voltage variations across other parallel circuits on other circuit boards already coupled to a power supply (PS), i.e. with charged input capacitors, when the present circuit board is newly coupled to this power supply or source. This is done by first intercoupling the parallel circuit and the source via a resistance and meanwhile preventing the clock signal (CK) from being applied to the electronic circuit (IC), and by allowing this clock signal to be applied to the electronic circuit (IC) during gradually increasing time periods (Th) after the resistance has been short-circuited.

    Abstract translation: 一种用于承载并联电路的电路板的电流控制电路,包括由CMOS器件分离的输入电容器(Cb),该输入电容器(Cb)由不向其施加时钟信号(CK)而不耗散功率的CMOS器件分配。 当本电路板新耦合到该电源或源时,该控制电路限制已经耦合到电源(PS)的其它电路板上的其它并联电路上的电压变化,即,具有充电的输入电容器。 这是通过首先通过电阻将并联电路和源极并联,同时防止时钟信号(CK)施加到电子电路(IC),并且通过将该时钟信号施加到电子电路(IC )在电阻短路后逐渐增加的时间段(Th)。

    COMMUNICATION SWITCHING ELEMENT AND METHOD FOR TRANSMITTING VARIABLE LENGTH CELLS
    4.
    发明申请
    COMMUNICATION SWITCHING ELEMENT AND METHOD FOR TRANSMITTING VARIABLE LENGTH CELLS 审中-公开
    通信切换元件和发送可变长度细胞的方法

    公开(公告)号:WO1991002420A1

    公开(公告)日:1991-02-21

    申请号:PCT/EP1989000942

    申请日:1989-08-09

    CPC classification number: H04L12/5601 H04L49/108 H04L49/608

    Abstract: The switching element is used for transferring, between X inputs (I1 - IX) and Y outputs (O1 - OY), cells divided into subcells of which only the first contains information about the destination output(s) of the cell. This switching element includes: a buffer memory (BM) with a plurality (C) of memory locations each having an address (K); and a memory management means (BMMU) for providing (FMLMC) addresses of free memory locations for storing the subcells therein, and for storing (BQ1 - BQY, SLM), under the form of linked lists, the memory location addresses used by the subcells, each list being associated to a distinct cell. The method is adapted to process variable length cells divided into subcells each containing a header (SCH) to distinguish a first/last subcell (FSC/LSC) of a cell from other subcells (ISC, LSC). Use is made of a subcell logic (SL) to detect the succession in either order of a subcell pertaining to a cell and of either a first/last subcell (FSC/LSC) of another cell or an idle subcell so as to identify the last/first subcell (LSC/FSC) of a cell.

    VOLTAGE SELECTOR AND COMPARATOR USED THEREWITH
    5.
    发明申请
    VOLTAGE SELECTOR AND COMPARATOR USED THEREWITH 审中-公开
    电压选择器和使用的比较器

    公开(公告)号:WO1990012324A1

    公开(公告)日:1990-10-18

    申请号:PCT/EP1989000343

    申请日:1989-04-01

    CPC classification number: H03K17/693 G01R19/0038 H03K5/2481

    Abstract: A voltage selector uses a comparator (COMP) in order to clamp the potential (VSUB) of a p-doped substrate of a telecommunication Subscriber Line Integrated Circuit to the most negative voltage appearing at two input terminals (V1/2), one being supplied with the battery voltage and the other with a synthesized voltage, both varying within a relatively wide range with either one being able to be more negative than the other. With V1/2 connected to VSUB through respective DMOS transistors (N1/2), V1/2 also constitute the inputs of COMP whose outputs (C1/2) are connected to the gates of the DMOS transistors. The comparator is so designed as to allow a fast change-over of the opposite conductivity states of N1 and N2 whenever there is an inversion in the relative magnitudes of the V1 and V2 voltages, the voltage drop over a conductive N1/2 transistor being much lower than in the case of clamping diodes.

    Abstract translation: 电压选择器使用比较器(COMP)来将电信用户线路集成电路的p掺杂衬底的电位(VSUB)钳位到出现在两个输入端子(V1 / 2)处的最负电压,一个被提供 电池电压和另一个具有合成电压,两者都在相对宽的范围内变化,任一个都能够比另一个更负。 V1 / 2通过相应的DMOS晶体管(N1 / 2)连接到VSUB,V1 / 2也构成输出(C1 / 2)连接到DMOS晶体管的栅极的COMP的输入。 比较器被设计成允许N1和N2的相反导电状态的快速切换,只要V1和V2电压的相对幅度都有反转,则导通的N1 / 2晶体管的电压降很大 低于钳位二极管的情况。

    PHASE SHIFTER
    6.
    发明申请
    PHASE SHIFTER 审中-公开
    相变器

    公开(公告)号:WO1991010286A1

    公开(公告)日:1991-07-11

    申请号:PCT/EP1989001614

    申请日:1989-12-27

    CPC classification number: H03H11/22 H03H11/18

    Abstract: In this phase shifter from an input signal (IN) two intermediate signals (V1, V2) are derived with a mutual phase shift of about 90 degrees. These signals (V1, V2) are then converted in two other signals (V3, V4) with equal amplitudes and from the latter signals (V3, V4) sum (V5) and difference (V6) signals are then generated and converted again in two signals (OUT1, OUT2) with equal amplitudes. These signals constitute the output signals.

    Abstract translation: 在来自输入信号(IN)的这个移相器中,两个中间信号(V1,V2)以大约90度的相位相移导出。 然后将这些信号(V1,V2)以相等幅度的两个其它信号(V3,V4)转换,然后从后面的信号(V3,V4)和(V5)和差(V6)信号中产生并再次转换成两个信号 信号(OUT1,OUT2)具有相等的幅度。 这些信号构成输出信号。

    RESEQUENCING SYSTEM FOR A SWITCHING NODE
    7.
    发明申请
    RESEQUENCING SYSTEM FOR A SWITCHING NODE 审中-公开
    一种切换节点的调度系统

    公开(公告)号:WO1991002419A1

    公开(公告)日:1991-02-21

    申请号:PCT/EP1989000941

    申请日:1989-08-09

    CPC classification number: H04L49/3081 H04L49/252 H04L49/30 H04L2012/565

    Abstract: Resequencing system for a switching node (SN) of a cell switching system wherein cells or packets, of fixed or variable length, transmitted from an input to an output of a switching network (SNW), are subjected in the network to variable initial time delays for instance because they follow different paths therein. To restore at the output the sequence with which the cells were supplied to the input, the cells at the output are subjected to additional variable complementary time delays which are so chosen that for each cell the sum of the two time delays is substantially equal to a predetermined total value.

    Abstract translation: 用于小区交换系统的交换节点(SN)的重新排序系统,其中从网络(SNW)的输入到输出的传输的固定或可变长度的小区或分组在网络中经受可变的初始时间延迟 例如因为它们遵循不同的路径。 为了在输出端恢复将单元提供给输入的序列,输出端的单元经受额外的可变互补时间延迟,这些时间延迟被选择为使得对于每个单元,两个时间延迟的总和基本上等于 预定总价值。

    COMMUNICATION SYSTEM
    8.
    发明申请
    COMMUNICATION SYSTEM 审中-公开
    通讯系统

    公开(公告)号:WO1991000662A1

    公开(公告)日:1991-01-10

    申请号:PCT/EP1989000728

    申请日:1989-06-23

    CPC classification number: H04L12/28

    Abstract: This system includes a main station (MS) and a plurality of substations (SX/SZ) which include each a transceiver and are all connected in parallel to first (UL) and second (DL) unidirectional links on which recurrent first and second cells of fixed length are transmitted in opposite direction. Each of these cells contains a plurality of signalling channels smaller than the number of substations. When a substation has to transmit data it starts an allocation procedure wherein the substation cooperates with the main station and by which a channel is allocated to it. Afterwards prior to transmitting the data the substation transmits a request signal in the allocated channel and starts transmission after having received from the main station a grant signal in the homologous signalling channel of a second cell. De-allocation of a channel occurs as soon as the latter is no longer needed.

    Abstract translation: 该系统包括主站(MS)和多个变电站(SX / SZ),其包括每个收发机,并且都与第一(UL)和第二(DL)单向链路并行连接,在该第一(UL)和第二(DL)单向链路上, 固定长度以相反方向传输。 这些单元中的每一个包含小于变电站数量的多个信令信道。 当变电站必须传输数据时,它开始一个分配程序,其中变电站与主站协作并通过其分配信道。 之后,在发送数据之前,变电站在分配的信道中发送请求信号,并且在从主站接收到在第二小区的同源信令信道中的授权信号之后开始发送。 只要不再需要信道,就会发生信道的解除分配。

    COMMUNICATION SWITCHING SYSTEM
    9.
    发明申请
    COMMUNICATION SWITCHING SYSTEM 审中-公开
    通信交换系统

    公开(公告)号:WO1990007832A1

    公开(公告)日:1990-07-12

    申请号:PCT/EP1988001214

    申请日:1988-12-24

    Abstract: In this system STM (Synchronous Transfer Mode) and ATM (Asynchronous Transfer Mode) cell streams are supplied to corresponding STM and ATM switching exchanges STME and ATME via the cascade connection of a multiplexer (MUX), a transmission link (L1) and a demultiplexer (DMUX). The MUX and DMUX are each constituted by a switching element with a plurality of inputs (I1/2; 13) and outputs (03, 04/5) coupled to a common switching means (SB1, TM1; SB2, TM2) via respective receiver (RC1/3) and transmitter (TC1/3) circuits. The common switching means samples the input cell streams at a frequency at least equal to the sum of the time slot frequencies of the time frames of the input cell streams. The time frames of the input and output cell streams are phase synchronous and the sampling of the input cell streams is performed in a predetermined order. The cells of the resultant (STM/ATM) cell stream are supplied to the transmitter circuits in function of their destination.

    Abstract translation: 在该系统中,STM(同步传输模式)和ATM(异步传输模式)信元流经由多路复用器(MUX),传输链路(L1)和解复用器(L1)的级联连接提供给相应的STM和ATM交换交换机STME和ATME (DMUX)。 MUX和DMUX各自由具有多个输入(I1 / 2; 13)的开关元件和经由相应接收器耦合到公共开关装置(SB1,TM1; SB2,TM2)的输出(03,04 / 5)构成; (RC1 / 3)和发射机(TC1 / 3)电路。 公共切换装置以至少等于输入单元流的时间帧的时隙频率之和的频率对输入单元流进行采样。 输入和输出单元流的时间帧是相位同步的,并且以预定顺序执行输入单元流的采样。 所得到的(STM / ATM)单元流的单元以其目的地的功能被提供给发射机电路。

    COMMUNICATION SWITCHING SYSTEM
    10.
    发明申请
    COMMUNICATION SWITCHING SYSTEM 审中-公开
    通信交换系统

    公开(公告)号:WO1990010984A1

    公开(公告)日:1990-09-20

    申请号:PCT/EP1989000281

    申请日:1989-03-14

    Abstract: Communication switching system wherein for each cell stream to be transmitted through a switching element a virtual path is established from an input link to an output link of this element on the basis of the individual bandwidth used by this cell stream and of the then calculated total bandwidth used on this output link. For each cell stream a maintenance cell containing the individual cell stream bandwidth is transmitted on the corresponding virtual path and by means of these maintenance cells the total bandwidth used on each output link is re-calculated and it is checked if it is equal to the above-mentioned calculated total bandwidth. The latter is adjusted if a difference is detected.

    Abstract translation: 通信交换系统,其中对于要通过交换元件发送的每个信元流,根据该信元流使用的单独带宽和随后计算出的总带宽,从输入链路到该元件的输出链路建立虚拟路径 用于此输出链接。 对于每个小区流,包含单个小区流带宽的维护单元在相应的虚拟路径上传输,并且通过这些维护单元重新计算每个输出链路上使用的总带宽,并且检查其是否等于上述 计算总带宽。 如果检测到差异,则调整后者。

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