公开(公告)号：WO2013101111A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067935

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  VARGAS, Jose (Andy), A. ,  KUMAR, Mohan, J. ,  CROSSLAND, James, B. ,  NACHIMUTHU, Murugasamy (Sammy), K. ,  YIGZAW, Theodros (Theo)

Inventor： VARGAS, Jose (Andy), A. ,  KUMAR, Mohan, J. ,  CROSSLAND, James, B. ,  NACHIMUTHU, Murugasamy (Sammy), K. ,  YIGZAW, Theodros (Theo)

IPC: G06F11/22 ,  G06F11/08 ,  G06F15/80

CPC classification number: G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

Abstract translation: 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：WO2013101053A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067829

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  CROSSLAND, James B. ,  OPFERMAN, Toby ,  FANNING, Blaise

Inventor： CROSSLAND, James B. ,  OPFERMAN, Toby ,  FANNING, Blaise

IPC: G06F12/02 ,  G06F13/16 ,  G11C13/02

CPC classification number: G06F12/0638 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0866 ,  G06F2212/202 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0036 ,  G11C14/0045

Abstract: A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.

Abstract translation: 公开了一种方法和系统。 在一个实施例中，该方法包括在相变存储器和交换机（PCMS）存储器内分配若干存储器位置，以用作随机存取存储器（RAM）盘。 RAM磁盘创建为由计算机系统中运行的软件应用程序使用。 该方法还包括将分配的PCMS存储器的至少一部分映射到软件应用地址空间。 最后，该方法还允许软件应用直接访问PCMS存储器的分配量的至少一部分。

公开(公告)号：WO2009032757A3

公开(公告)日：2009-05-07

申请号：PCT/US2008074638

申请日：2008-08-28

Applicant: INTEL CORP ,  KAUSHKI SHIVNANDAN D ,  TIRUVALLUR KESHAVAN K ,  CROSSLAND JAMES B ,  MUTHRASANALLUR SRIDHAR ,  PARTHASARATHY RAJESH S ,  HOOD LUKE P

Inventor： KAUSHKI SHIVNANDAN D ,  TIRUVALLUR KESHAVAN K ,  CROSSLAND JAMES B ,  MUTHRASANALLUR SRIDHAR ,  PARTHASARATHY RAJESH S ,  HOOD LUKE P

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract translation: 在一些实施例中，一种装置包括逻辑中断识别号码创建逻辑，以接收物理处理器识别号码并通过使用物理处理器识别号码创建逻辑处理器识别号码。 每个逻辑处理器识别号码对应于物理处理器识别号码中的一个，并且逻辑处理器识别号码每个包括处理器簇识别号码和簇内识别号码。 处理器集群标识号每一个被形成为包括来自对应的位置的相应物理处理器标识号的一组比特，并且每个集群内标识号都是响应于对应物理处理器标识的其他比特的值而形成的 数。 描述了其他实施例。

公开(公告)号：CA755021A

公开(公告)日：1967-03-21

申请号：CA755021D

Applicant: CROSSLAND JAMES B

Inventor： CROSSLAND JAMES B