公开(公告)号：WO2013100992A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067646

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  MISHAELI, Michael ,  CROSSLAND, James, B. ,  GINZBURG, Boris ,  WEISSMAN, Eliezer

Inventor： MISHAELI, Michael ,  CROSSLAND, James, B. ,  GINZBURG, Boris ,  WEISSMAN, Eliezer

IPC: G06F9/06 ,  G06F9/30 ,  G06F15/76

CPC classification number: G06F9/461 ,  G06F9/44 ,  G06F9/445 ,  G06F9/46 ,  G06F9/48

Abstract: Extended features such as registers and functions within processors are made available to operating systems (OS) using an extended-state driver and by modifying instruction set extensions, such as XSAVE. A map-table designates a correspondence between memory locations for storing data relating to extended features not supported by the OS and called by an application. As a result, applications may utilize processor resources which are unsupported by the OS.

Abstract translation: 扩展功能（如处理器内的寄存器和功能）可以使用扩展状态驱动程序和修改指令集扩展（如XSAVE）对操作系统（OS）可用。 映射表指定用于存储与OS不支持并被应用程序调用的扩展特征有关的数据的存储器位置之间的对应关系。 因此，应用程序可能利用OS不支持的处理器资源。

公开(公告)号：WO2014197310A1

公开(公告)日：2014-12-11

申请号：PCT/US2014/040209

申请日：2014-05-30

Applicant: INTEL CORPORATION ,  PATEL, Baiju V. ,  LI, Xiaoning ,  ANVIN, H. P. ,  MALLICK, Asit K. ,  NEIGER, Gilbert ,  CROSSLAND, James B. ,  OPFERMAN, Toby ,  KHARE, Atul A. ,  BRANDT, Jason W. ,  COKE, James S. ,  VAJDA, Brian L.

Inventor： PATEL, Baiju V. ,  LI, Xiaoning ,  ANVIN, H. P. ,  MALLICK, Asit K. ,  NEIGER, Gilbert ,  CROSSLAND, James B. ,  OPFERMAN, Toby ,  KHARE, Atul A. ,  BRANDT, Jason W. ,  COKE, James S. ,  VAJDA, Brian L.

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

Abstract: An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Abstract translation: 示例处理系统可以包括：下堆叠绑定寄存器，被配置为存储第一存储器地址，第一存储器地址识别经由堆栈段可寻址的存储器的下限; 上堆叠绑定寄存器，其被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 并且通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来配置用于检测未授权堆栈枢转的堆栈边界检查逻辑。

公开(公告)号：WO2013016345A3

公开(公告)日：2013-01-31

申请号：PCT/US2012/047991

申请日：2012-07-24

Applicant: INTEL CORPORATION ,  SANKARAN, Rajesh M. ,  KOKER, Altug ,  LANTZ, Philip ,  MALLICK, Asit K. ,  CROSSLAND, James B. ,  NAVALE, Aditva ,  NEIGER, Gilbert ,  ANDERSON, Andrew V.

Inventor： SANKARAN, Rajesh M. ,  KOKER, Altug ,  LANTZ, Philip ,  MALLICK, Asit K. ,  CROSSLAND, James B. ,  NAVALE, Aditva ,  NEIGER, Gilbert ,  ANDERSON, Andrew V.

IPC: G06F12/10 ,  G06F15/80

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

公开(公告)号：WO2012087446A1

公开(公告)日：2012-06-28

申请号：PCT/US2011/060011

申请日：2011-11-09

Applicant: INTEL CORPORATION ,  PATEL, Baiju V. ,  NEIGER, Gilbert ,  DIXON, Martin G. ,  COKE, James S. ,  CROSSLAND, James B.

Inventor： PATEL, Baiju V. ,  NEIGER, Gilbert ,  DIXON, Martin G. ,  COKE, James S. ,  CROSSLAND, James B.

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/30032 ,  G06F9/30101 ,  G06F9/342

Abstract: Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

Abstract translation: 描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。 一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器 写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

公开(公告)号：WO2014105150A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046907

申请日：2013-06-20

Applicant: INTEL CORPORATION ,  CONRAD, Shaun M. ,  FENGER, Russell J. ,  KHANNA, Gaurav ,  SETH, Rahul ,  CROSSLAND, James B. ,  AGGARWAL, Anil

Inventor： CONRAD, Shaun M. ,  FENGER, Russell J. ,  KHANNA, Gaurav ,  SETH, Rahul ,  CROSSLAND, James B. ,  AGGARWAL, Anil

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F1/3206 ,  G06F2212/683 ,  Y02D10/13

Abstract: A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.

Abstract translation: 描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。 该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。 该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。

公开(公告)号：WO2013048490A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054414

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  PUTHIYEDATH, Leena, K. ,  FANNING, Blaise ,  OPFERMAN, Tony ,  CROSSLAND, James, B.

Inventor： PUTHIYEDATH, Leena, K. ,  FANNING, Blaise ,  OPFERMAN, Tony ,  CROSSLAND, James, B.

IPC: G06F12/00 ,  G06F13/14 ,  G06F13/16

CPC classification number: G06F3/0679 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0644 ,  G06F12/00 ,  G06F12/0238 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1004 ,  G06F2212/1056 ,  G06F2212/2024 ,  G06F2212/214 ,  G06F2212/251 ,  G06F2212/7201

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte -rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色，特别是替换可由I / O访问的传统大容量存储。 计算机系统包括执行软件的处理器和耦合到处理器的存储器。 存储器的至少一部分包括由处理器字节可刷新和字节可擦除的非易失性随机存取存储器（NVRAM）。 该系统还包括耦合到NVRAM的存储器控​​制器，以响应于来自软件的访问大容量存储器的请求来执行存储器访问操作以访问NVRAM。

公开(公告)号：WO2013016345A2

公开(公告)日：2013-01-31

申请号：PCT/US2012047991

申请日：2012-07-24

Applicant: INTEL CORP ,  SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

Inventor： SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

IPC: G06F12/10 ,  G06F15/80

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Abstract translation: 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

公开(公告)号：WO2010062514A3

公开(公告)日：2010-07-22

申请号：PCT/US2009061641

申请日：2009-10-22

Applicant: INTEL CORP ,  TIRUVALLUR KESHAVAN ,  PARTHASARATHY RAJESH ,  CROSSLAND JAMES B ,  KAUSHIK SHIVNANDAN ,  HOOD LUKE

Inventor： TIRUVALLUR KESHAVAN ,  PARTHASARATHY RAJESH ,  CROSSLAND JAMES B ,  KAUSHIK SHIVNANDAN ,  HOOD LUKE

IPC: G06F13/24 ,  G06F13/20 ,  G06F13/38

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation: 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（APIC）通过使用各种接口指令或操作的APIC接口寄存器内的一组位进行接口，而不使用存储器映射的输入/输出（MMIO）。

公开(公告)号：WO2010062514A2

公开(公告)日：2010-06-03

申请号：PCT/US2009/061641

申请日：2009-10-22

Applicant: INTEL CORPORATION ,  TIRUVALLUR, Keshavan ,  PARTHASARATHY, Rajesh ,  CROSSLAND, James B. ,  KAUSHIK, Shivnandan ,  HOOD, Luke

Inventor： TIRUVALLUR, Keshavan ,  PARTHASARATHY, Rajesh ,  CROSSLAND, James B. ,  KAUSHIK, Shivnandan ,  HOOD, Luke

IPC: G06F13/24 ,  G06F13/20 ,  G06F13/38

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation:

一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，在不使用存储器映射输入/输出（MMIO）的情况下，使用各种接口指令或操作经由APIC接口寄存器内的一组比特来接口高级可编程中断控制器（APIC）。

公开(公告)号：WO2009032757A2

公开(公告)日：2009-03-12

申请号：PCT/US2008/074638

申请日：2008-08-28

Applicant: INTEL CORPORATION ,  KAUSHKI, Shivnandan D. ,  TIRUVALLUR, Keshavan K. ,  CROSSLAND, James B. ,  MUTHRASANALLUR, Sridhar ,  PARTHASARATHY, Rajesh S. ,  HOOD, Luke P.

Inventor： KAUSHKI, Shivnandan D. ,  TIRUVALLUR, Keshavan K. ,  CROSSLAND, James B. ,  MUTHRASANALLUR, Sridhar ,  PARTHASARATHY, Rajesh S. ,  HOOD, Luke P.

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

Abstract translation: 在一些实施例中，装置包括用于接收物理处理器标识号的逻辑中断识别号码创建逻辑，并通过使用物理处理器标识号创建逻辑处理器标识号。 每个逻辑处理器识别号对应于物理处理器识别号之一，并且逻辑处理器标识号各自包括处理器群标识号和群内标识号。 每个处理器集群标识号被形成为包括从相应的物理处理器标识号码位置移位的一组位，并且群内标识号分别响应于对应的物理处理器标识的其他位的值而形成 数。 描述其他实施例。