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    MRAM DEVICE INTEGRATED WITH OTHER TYPES OF CIRCUITRY
    11.
    发明申请
    MRAM DEVICE INTEGRATED WITH OTHER TYPES OF CIRCUITRY 审中-公开
    与其他类型电路集成的MRAM器件

    公开(公告)号：WO2005060439A2

    公开(公告)日：2005-07-07

    申请号：PCT/US2004/036290

    申请日：2004-10-29

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  KERSZYKOWSKI, Gloria J. ,  CHANG, Li Hsin ,  DURLAM, Mark A. ,  LIEN, Mitchell T. ,  MEIXNER, Thomas V. ,  WISE, Loren J.

    Inventor： KERSZYKOWSKI, Gloria J. ,  CHANG, Li Hsin ,  DURLAM, Mark A. ,  LIEN, Mitchell T. ,  MEIXNER, Thomas V. ,  WISE, Loren J.

    IPC: G11C11/15

    CPC classification number: G11C11/15

    Abstract: A magnetoresistive random access memory (MRAM) (13) is embedded with another circuit type (12). Logic (12), such as a processing unit, is particularly well-suited circuit type for embedding with MRAM (13). The embedding is made more efficient by using a metal layer (26) that is used as part of the interconnect for the other circuit (12) also as part of the MRAM cell (13). The MRAM cells (13) are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line (26) that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic (12).

    Abstract translation: 磁阻随机存取存储器（MRAM）（13）被嵌入另一电路类型（12）。 诸如处理单元的逻辑（12）特别适用于用MRAM（13）嵌入的电路类型。 通过使用也作为MRAM单元（13）的一部分而用作另一电路（12）的互连的一部分的金属层（26），嵌入更加有效。 MRAM单元（13）全部由程序行写成，它们是两条线，用于定义要写入的单元格。 因此，简化了设计，因为对于用于MRAM的程序行之一和用于逻辑（12）的互连线之一的金属线（26）的使用是共同的。

    MRAM EMBEDDED SMART POWER INTEGRATED CIRCUITS
    15.
    发明申请
    MRAM EMBEDDED SMART POWER INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：WO2007005303A3

    公开(公告)日：2007-01-11

    申请号：PCT/US2006/024228

    申请日：2006-06-22

    Applicant: FREESCALE SEMICONDUCTOR ,  GRYNKEWICH, Gregory W. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  SALTER, Eric J.

    Inventor： GRYNKEWICH, Gregory W. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  SALTER, Eric J.

    IPC: G11C11/00

    Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture and a smart power integrat circuit architecture formed on the same substrate (302) using the same fabrication process technology The fabrication process technology is a modular process having a front end process and a back end process In the example embodiment, the smart power architecture includes a power circuit component (304), a digital logic component (306), and an analog control component (312) form by the front end process, and a sensor architecture (308) formed by the back end process The MRAM architecture (310) includes an MRAM circuit component (314) formed by the front end process and an MRAM cell array (316) formed by the back end process In one practical embodiment, the sensor architecture (308) includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array (316).

    METHODS FOR CONTRACTING CONDUCTING LAYERS OVERLYING MAGNETOELECTRONIC ELEMENTS OF MRAM DEVICES
    16.
    发明申请
    METHODS FOR CONTRACTING CONDUCTING LAYERS OVERLYING MAGNETOELECTRONIC ELEMENTS OF MRAM DEVICES 审中-公开
    收缩MRAM器件的磁电子元件的导电层的方法

    公开(公告)号：WO2004095515B1

    公开(公告)日：2005-03-17

    申请号：PCT/US2004011872

    申请日：2004-04-16

    Applicant: FREESCALE SEMICONDUCTOR INC ,  GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J

    Inventor： GRYNKEWICH GREGORY W ,  BUTCHER BRIAN R ,  DURLAM MARK A ,  KYLER KELLY ,  SNYDER CHARLES A ,  SMITH KENNETH H ,  TRACY CLARENCE J ,  WILLIAMS RICHARD

    IPC: G11C11/15 ,  H01L21/8246 ,  H01L43/12 ,  G11C8/02 ,  G11C11/00 ,  H01L43/00

    CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer (26) is deposited overlying the memory element layer (18). A first dielectric layer (28) is deposited overlying the first electrically conductive layer (26) and is patterned and etched to form a first masking layer (28). Using the first masking layer (28), the first electrically conductive layer (26) is etched. A second dielectric layer (36) is deposited overlying the first masking layer (28) and the dielectric region. A portion of the second dielectric layer (36) is removed to expose the first masking layer (28). The second dielectric layer (36) and the first masking layer (28) are subjected to an etching chemistry such that the first masking layer (28) is etched at a faster rate than the second dielectric layer (36). The etching exposes the first electrically conductive layer (26).

    Abstract translation: 用于接触覆盖磁电元件的导电层的方法包括形成覆盖介电区域的存储元件层。 沉积第一导电层（26），覆盖存储元件层（18）。 沉积覆盖第一导电层（26）的第一介电层（28），并将其图案化并蚀刻以形成第一掩模层（28）。 使用第一掩模层（28），蚀刻第一导电层（26）。 沉积覆盖第一掩模层（28）和介电区域的第二介电层（36）。 第二电介质层（36）的一部分被去除以暴露第一掩模层（28）。 对第二介电层（36）和第一掩模层（28）进行蚀刻化学处理，使得以比第二介电层（36）更快的速率蚀刻第一掩模层（28）。 蚀刻暴露第一导电层（26）。

    MAGNETORESISTIVE RANDOM ACESS MEMORY DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME
    17.
    发明申请
    MAGNETORESISTIVE RANDOM ACESS MEMORY DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME 审中-公开
    磁阻随机存储器件结构及其制造方法

    公开(公告)号：WO2004095459A2

    公开(公告)日：2004-11-04

    申请号：PCT/US2004/011864

    申请日：2004-04-16

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  GRYNKEWICH, Gregory ,  DEHERRERA, Mark ,  DURLAM, Mark, A. ,  TRACY, Clarence, J.

    Inventor： GRYNKEWICH, Gregory ,  DEHERRERA, Mark ,  DURLAM, Mark, A. ,  TRACY, Clarence, J.

    IPC: G11C

    CPC classification number: H01L27/228 ,  B82Y10/00

    Abstract: A method for fabricating an MRAM device structure (10) includes providing a substrate (12) on which is formed a first transistor (14) and a second transistor (14). An operative memory element device (60) is formed in electrical contact with the first transistor (14). At least a portion of a false memory element device (58) is formed in electrical contact with the second transistor (14). A first dielectric layer (62) is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via (66) to the at least a portion of a false memory element device (58) and a second via (64) to the operative memory element device (60). An electrically conductive interconnect layer (68) is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device (58) to the operative memory element device (64).

    Abstract translation: 一种用于制造MRAM器件结构（10）的方法包括提供其上形成有第一晶体管（14）和第二晶体管（14）的衬底（12）。 操作存储元件装置（60）形成为与第一晶体管（14）电接触。 假存储元件器件（58）的至少一部分形成为与第二晶体管（14）电接触。 第一介电层（62）沉积在伪存储元件装置和操作存储元件装置的至少一部分上。 第一介电层被蚀刻以同时形成第一通孔（66）到伪存储元件器件（58）的至少一部分和第二通孔（64）到操作存储元件器件（60）。 沉积导电互连层（68），使得导电互连层从假存储元件装置（58）的至少一部分延伸到可操作存储元件装置（64）。

    3-D INDUCTOR AND TRANSFORMER DEVICES IN MRAM EMBEDDED INTEGRATED CIRCUITS
    18.
    发明申请
    3-D INDUCTOR AND TRANSFORMER DEVICES IN MRAM EMBEDDED INTEGRATED CIRCUITS 审中-公开
    MRAM嵌入式集成电路中的3-D电感器和变压器器件

    公开(公告)号：WO2006132750A3

    公开(公告)日：2007-11-01

    申请号：PCT/US2006017689

    申请日：2006-05-09

    Applicant: FREESCALE SEMICONDUCTOR INC ,  DURLAM MARK A ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  ENGEL BRADLEY N

    Inventor： DURLAM MARK A ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  ENGEL BRADLEY N

    IPC: G11C11/14

    CPC classification number: H01L27/222 ,  G11C11/16 ,  H01F17/0006 ,  H01F19/04 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture (310) and at least one inductance element (3 12, 3 14) formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture (310) and the inductance element (312, 314) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

    Abstract translation: 集成电路器件（300）包括磁性随机存取存储器（“MRAM”）结构（310）和使用相同的制造工艺技术形成在同一衬底上的至少一个电感元件（31,23）。 可以是电感器或变压器的电感元件形成在与MRAM架构的程序行相同的金属层（或多层）上。 除了编程线层之外，可以将任何可用的金属层添加到电感元件以提高其效率。 MRAM架构（310）和电感元件（312,314）的并行制造有助于在衬底的有源电路块上可用的物理空间的有效且成本有效的使用，导致三维集成。

    MRAM DEVICE INTEGREATED WITH OTHER CIRCUITRY
    19.
    发明申请
    MRAM DEVICE INTEGREATED WITH OTHER CIRCUITRY 审中-公开
    MRAM设备与其他电路集成

    公开(公告)号：WO2005060439A3

    公开(公告)日：2007-05-24

    申请号：PCT/US2004036290

    申请日：2004-10-29

    Applicant: FREESCALE SEMICONDUCTOR INC ,  KERSZYKOWSKI GLORIA J ,  CHANG LI HSIN ,  DURLAM MARK A ,  LIEN MITCHELL T ,  MEIXNER THOMAS V ,  WISE LOREN J

    Inventor： KERSZYKOWSKI GLORIA J ,  CHANG LI HSIN ,  DURLAM MARK A ,  LIEN MITCHELL T ,  MEIXNER THOMAS V ,  WISE LOREN J

    IPC: G11C7/00 ,  G11C11/15

    CPC classification number: G11C11/15

    Abstract: A magnetoresistive random access memory (MRAM) (13) is embedded with another circuit type (12). Logic (12), such as a processing unit, is particularly well-suited circuit type for embedding with MRAM (13). The embedding is made more efficient by using a metal layer (26) that is used as part of the interconnect for the other circuit (12) also as part of the MRAM cell (13). The MRAM cells (13) are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line (26) that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic (12).

    Abstract translation: 磁阻随机存取存储器（MRAM）（13）被嵌入另一电路类型（12）。 诸如处理单元的逻辑（12）特别适用于用MRAM（13）嵌入的电路类型。 通过使用也作为MRAM单元（13）的一部分而用作另一电路（12）的互连的一部分的金属层（26），嵌入更加有效。 MRAM单元（13）全部由程序行写成，它们是两条线，用于定义要写入的单元格。 因此，简化了设计，因为对于用于MRAM的程序行之一和用于逻辑（12）的互连线之一的金属线（26）的使用是共同的。

    METHODS OF IMPLEMENTING MAGNETIC TUNNEL JUNCTION CURRENT SENSORS
    20.
    发明申请
    METHODS OF IMPLEMENTING MAGNETIC TUNNEL JUNCTION CURRENT SENSORS 审中-公开
    实施磁性隧道结电流传感器的方法

    公开(公告)号：WO2007053341A2

    公开(公告)日：2007-05-10

    申请号：PCT/US2006/041148

    申请日：2006-10-20

    Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A.

    Inventor： CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A.

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  H01L27/228

    Abstract: An integrated circuit device (800) is provided which comprises a substrate (801), a conductive line (807) configured to experience a pressure, and a magnetic tunnel junction ("MTJ") core (802) formed between the substrate and the current line. The conductive line (807) is configured to move in response to the pressure, and carries a current which generates a magnetic field. The MTJ core (802) has a resistance value which varies based on the magnetic field. The resistance of the MTJ core (802) therefore varies with respect to changes in the pressure. The MTJ core (802) is configured to produce an electrical output signal which varies as a function of the pressure.

    Abstract translation: 提供集成电路器件（800），其包括衬底（801），被配置为经历压力的导线（807）和磁隧道结（“MTJ”）芯（ 802）形成在衬底和电流线之间。 导线（807）被配置为响应于压力而移动，并且承载产生磁场的电流。 MTJ芯（802）具有基于磁场而变化的电阻值。 MTJ芯（802）的电阻因此相对于压力的变化而变化。 MTJ核心（802）被配置为产生电输出信号，其随着压力而变化。

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