公开(公告)号：WO2007133280A3

公开(公告)日：2007-11-22

申请号：PCT/US2006/060826

申请日：2006-11-13

Applicant: FREESCALE SEMICONDUCTOR INC. ,  DE FRESART, Edouard, D. ,  BAIRD, Robert, W. ,  QIN, Ganming

Inventor： DE FRESART, Edouard, D. ,  BAIRD, Robert, W. ,  QIN, Ganming

IPC: H01L29/80

Abstract: Methods and apparatus are provided for TMOS devices (40), comprising multiple N-type source regions (50), electrically in parallel, located in multiple P-body regions (46) separated by N-type JFET regions (56) at a first surface. The gate (53) overlies the body channel regions (46) and the JFET region (56) lying between the body regions. The JFET region (56) communicates with an underlying drain region (42) via an N-epi region (44). Ion implantation and heat treatment are used to tailor the net active doping concentration N d in the JFET region (56) of length L acc and net active doping concentration N a in the P-body regions (46) of length L body so that a charge balance relationship (L body * N a ) = k 1 *(L acc * N d ) between P-body and JFET regions is satisfied, where k 1 is about 0.6 ≤ k 1 ≤ 1.4. The entire device (40) can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region (44) to the drain (42).

公开(公告)号：WO2007133280A2

公开(公告)日：2007-11-22

申请号：PCT/US2006060826

申请日：2006-11-13

Applicant: FREESCALE SEMICONDUCTOR INC ,  DE FRESART EDOUARD D ,  BAIRD ROBERT W ,  QIN GANMING

Inventor： DE FRESART EDOUARD D ,  BAIRD ROBERT W ,  QIN GANMING

IPC: H01L29/76

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/7809 ,  H01L29/7811

Abstract: Methods and apparatus are provided for TMOS devices (40), comprising multiple N-type source regions (50), electrically in parallel, located in multiple P-body regions (46) separated by N-type JFET regions (56) at a first surface. The gate (53) overlies the body channel regions (46) and the JFET region (56) lying between the body regions. The JFET region (56) communicates with an underlying drain region (42) via an N-epi region (44). Ion implantation and heat treatment are used to tailor the net active doping concentration N d in the JFET region (56) of length L acc and net active doping concentration N a in the P-body regions (46) of length L body so that a charge balance relationship (L body * N a ) = k 1 *(L acc * N d ) between P-body and JFET regions is satisfied, where k 1 is about 0.6 = k 1 = 1.4. The entire device (40) can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region (44) to the drain (42).

Abstract translation: 提供了用于TMOS器件（40）的方法和装置，其包括多个并联的N型源极区（50），位于由N型JFET区域（56）分开的多个P体区域（46）中，第一 表面。 栅极（53）覆盖在身体区域（46）和位于身体区域之间的JFET区域（56）之间。 JFET区域（56）经由N-epi区域（44）与下面的漏极区域（42）连通。 离子注入和热处理用于定制长度为L的JFET区域（56）中的净有源掺杂浓度N sub和净活性掺杂浓度N SUB 在长度为L本体的P体区域（46）中的一个，使得电荷平衡关系（L * N ]]>其中k≠1时，满足P体和JFET区域之间的距离（k）= k 1（N） 约为0.6 = k 1 = 1.4。 整个器件（40）可以使用平面技术制造，并且电荷平衡区域不需要延伸穿过下面的N外延区域（44）到漏极（42）。

公开(公告)号：WO2007053341A3

公开(公告)日：2007-11-15

申请号：PCT/US2006041148

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A

IPC: G11C11/14

CPC classification number: H01L43/12 ,  H01L27/228

Abstract: An integrated circuit device (800) is provided which comprises a substrate (801), a conductive line (807) configured to experience a pressure, and a magnetic tunnel junction ("MTJ") core (802) formed between the substrate and the current line. The conductive line (807) is configured to move in response to the pressure, and carries a current which generates a magnetic field. The MTJ core (802) has a resistance value which varies based on the magnetic field. The resistance of the MTJ core (802) therefore varies with respect to changes in the pressure. The MTJ core (802) is configured to produce an electrical output signal which varies as a function of the pressure.

Abstract translation: 提供了一种集成电路器件（800），其包括衬底（801），被配置为经受压力的导线（807）和形成在衬底和电流之间的磁性隧道结（“MTJ”）芯 线。 导线807配置为响应于压力移动，并且传送产生磁场的电流。 MTJ磁芯（802）具有基于磁场而变化的电阻值。 因此，MTJ芯（802）的电阻因压力变化而变化。 MTJ内核（802）被配置为产生作为压力的函数而变化的电输出信号。

公开(公告)号：WO2007053340A3

公开(公告)日：2007-05-10

申请号：PCT/US2006/041147

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  GRYNKEWICH, Gregory W. ,  SALTER, Eric J. ,  ZUO, Jiang-Kai

Inventor： CHUNG, Young Sir ,  BAIRD, Robert W. ,  DURLAM, Mark A. ,  GRYNKEWICH, Gregory W. ,  SALTER, Eric J. ,  ZUO, Jiang-Kai

IPC: G11C11/00

Abstract: An integrated circuit device (600) is provided which includes an active circuit component (604, 804) and a current sensor (602, 802). The active circuit component (604, 804) may be coupled between a first conductive layer (206) and a second conductive layer (210), and is configured to produce a first current. The current sensor (602, 802) is disposed over the active circuit component. The current sensor (602, 802) may comprise a Magnetic Tunnel Junction ("MTJ") core disposed between the first conductive layer (206) and the second conductive layer (210). The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

公开(公告)号：WO2007016009A3

公开(公告)日：2008-01-17

申请号：PCT/US2006028573

申请日：2006-07-24

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  GRYNKEWICH GREGORY W

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  GRYNKEWICH GREGORY W

IPC: G11B5/127

CPC classification number: G01R33/06 ,  H01L43/12 ,  Y10T29/49032 ,  Y10T29/49034 ,  Y10T29/49036 ,  Y10T29/49039 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044

Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus (30) comprises a magnetic tunnel junction (MTJ) [32] and a magnetic field source (34) whose magnetic field (35) overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield (33) is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes (36, 38) separated by a dielectric (37) configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

Abstract translation: 提供了用于感测物理参数的方法和装置。 该装置（30）包括一个磁性隧道结（MTJ）[32]和一个磁场源（34），其磁场（35）与MTJ重叠，并且其与MTJ的接近度响应于传感器的输入而变化。 至少在远离MTJ的MFS的面上设有磁屏蔽（33）。 MTJ包括由电介质（37）分开的第一和第二磁极（36,38），其被配置为允许它们之间的显着的隧道传导。 第一磁性区域的自旋轴被固定，第二磁极的自由轴自由。 磁场源比第一磁极更靠近第二磁极。 通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。

公开(公告)号：WO2007102885A3

公开(公告)日：2007-09-13

申请号：PCT/US2006/060208

申请日：2006-10-25

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHUNG, Young Sir ,  BAIRD, Robert W. ,  ENGEL, Bradley N.

Inventor： CHUNG, Young Sir ,  BAIRD, Robert W. ,  ENGEL, Bradley N.

IPC: G11B5/33

Abstract: An integrated circuit device (800) is provided which comprises a substrate (801), a conductive line (807) configured to experience a pressure, and a magnetic tunnel junction ("MTJ") core (802) formed between the substrate and the current line. The conductive line (807) is configured to move in response to the pressure, and carries a current which generates a magnetic field. The MTJ core (802) has a resistance value which varies based on the magnetic field. The resistance of the MTJ core (802) therefore varies with respect to changes in the pressure. The MTJ core (802) is configured to produce an electrical output signal which varies as a function of the pressure.

公开(公告)号：WO2007053340A2

公开(公告)日：2007-05-10

申请号：PCT/US2006041147

申请日：2006-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  GRYNKEWICH GREGORY W ,  SALTER ERIC J ,  ZUO JIANG-KAI

Inventor： CHUNG YOUNG SIR ,  BAIRD ROBERT W ,  DURLAM MARK A ,  GRYNKEWICH GREGORY W ,  SALTER ERIC J ,  ZUO JIANG-KAI

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

Abstract: An integrated circuit device (600) is provided which includes an active circuit component (604, 804) and a current sensor (602, 802). The active circuit component (604, 804) may be coupled between a first conductive layer (206) and a second conductive layer (210), and is configured to produce a first current. The current sensor (602, 802) is disposed over the active circuit component. The current sensor (602, 802) may comprise a Magnetic Tunnel Junction ("MTJ") core disposed between the first conductive layer (206) and the second conductive layer (210). The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

Abstract translation: 提供了一种集成电路装置（600），其包括有源电路部件（604,804）和电流传感器（602,802）。 有源电路组件（604,804）可以耦合在第一导电层（206）和第二导电层（210）之间，并且被配置为产生第一电流。 电流传感器（602,802）设置在有源电路部件上。 电流传感器（602,802）可以包括设置在第一导电层（206）和第二导电层（210）之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

公开(公告)号：WO2007016010A2

公开(公告)日：2007-02-08

申请号：PCT/US2006/028574

申请日：2006-07-24

Applicant: FREESCALE SEMICONDUCTOR ,  CHUNG, Young Sir ,  BAIRD, Robert W.

Inventor： CHUNG, Young Sir ,  BAIRD, Robert W.

IPC: G11B5/127 ,  G11B5/33

CPC classification number: G01R33/06 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098

Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus (30) comprises a magnetic tunnel junction (MTJ) [32] and a magnetic field source (34) whose magnetic field (35) overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield (33) is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes (36, 38) separated by a dielectric (37) configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

Abstract translation: 提供了用于感测物理参数的方法和装置。 该装置（30）包括一个磁性隧道结（MTJ）[32]和一个磁场源（34），其磁场（35）与MTJ重叠，并且其与MTJ的接近度响应于传感器的输入而变化。 至少在远离MTJ的MFS的面上设置磁屏蔽（33）。 MTJ包括由电介质（37）分开的第一和第二磁极（36,38），其被配置为允许它们之间的显着的隧道传导。 第一磁性区域的自旋轴被固定，第二磁极的自由轴自由。 磁场源比第一磁极更靠近第二磁极。 通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。

公开(公告)号：WO2006132750A2

公开(公告)日：2006-12-14

申请号：PCT/US2006/017689

申请日：2006-05-09

Applicant: FREESCALE SEMICONDUCTOR ,  DURLAM, Mark, A. ,  CHUNG, Young, Sir ,  BAIRD, Robert, W. ,  ENGEL, Bradley, N.

Inventor： DURLAM, Mark, A. ,  CHUNG, Young, Sir ,  BAIRD, Robert, W. ,  ENGEL, Bradley, N.

IPC: H01L43/00

CPC classification number: H01L27/222 ,  G11C11/16 ,  H01F17/0006 ,  H01F19/04 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device (300) includes a magnetic random access memory ("MRAM") architecture (310) and at least one inductance element (312, 314) formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture (310) and the inductance element (312, 314) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

Abstract translation: 集成电路器件（300）包括磁性随机存取存储器（“MRAM”）架构（310）和使用相同制造工艺技术形成在同一衬底上的至少一个电感元件（312,314）。 可以是电感器或变压器的电感元件形成在与MRAM架构的程序行相同的金属层（或多层）上。 除了编程线层之外，可以将任何可用的金属层添加到电感元件中以提高其效率。 MRAM架构（310）和电感元件（312,314）的并行制造有助于在衬底的有源电路块上可用的物理空间的有效且成本有效的使用，导致三维集成。

公开(公告)号：WO2006107384A1

公开(公告)日：2006-10-12

申请号：PCT/US2006/003530

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR ,  MIN, Won, Gi ,  BAIRD, Robert, W. ,  ZUO, Jiang-Kai ,  LEE, Gordon, P.

Inventor： MIN, Won, Gi ,  BAIRD, Robert, W. ,  ZUO, Jiang-Kai ,  LEE, Gordon, P.

IPC: H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.

Abstract translation: 具有位于有源区域（106）或底部电极正上方的栅电极（104）的端角（120,122）的反熔断元件（102）。 栅电极（104）和有源区（106）之间的最小编程电压产生通过位于它们之间的绝缘层（110）的电流路径。 在栅电极（104）的端角（120,122）处产生的高电场导致在端角（120,122）正下方的绝缘层（110）的破裂和破裂。 绝缘层（110）在拐角（120,122）处的定位提供较低的后编程电阻和变化，并且以较低的编程功率进行更快的编程。 当反熔丝元件（102）集成到阵列（300,320,400,550）中时，提供了增加的堆积密度。 阵列被制造为包括用于单个反熔丝元件（302）编程的多个有效区域（304）或用于多元件编程的公共有效区域（324,405,426,506）。