公开(公告)号：US20150156140A1

公开(公告)日：2015-06-04

申请号：US14622267

申请日：2015-02-13

Applicant: Force10 Networks, Inc.

Inventor： David K. Wong

IPC: H04L12/931 ,  G08B21/18

CPC classification number: H04L49/40 ,  G06F15/161 ,  G08B21/18 ,  H04J3/047 ,  H04J3/247 ,  H04L12/403

Abstract: A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

Abstract translation: 模块化系统分别在控制模块和每个端口模块上使用现场可编程门阵列（FPGA）之间的点对点通信，以管理模块的基本模块功能，如电源，环境监控和健康检查; 他们的组件。 这允许在不完全为每个卡供电的情况下对机箱进行管理，从而免除模块上的处理器进行健康检查，从而允许专用资源快速监控每张卡的运行状况，并防止一张坏卡禁用所有卡的管理。

公开(公告)号：US20030179049A1

公开(公告)日：2003-09-25

申请号：US10068622

申请日：2002-02-05

Applicant: Force10 Networks, Inc.

Inventor： Joel R. Goergen

IPC: H04B003/04

CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

公开(公告)号：WO2009017800A3

公开(公告)日：2009-02-05

申请号：PCT/US2008/009270

申请日：2008-07-31

Applicant: FORCE10 NETWORKS, INC.

Inventor： GOERGEN, Joel, R. ,  SUBRAMANIAN, Krishnamurthy ,  GUI, Ann

IPC: H04L25/03 ,  H04L25/49 ,  H04L25/14

Abstract: In one embodiment, a hybrid backplane coding scheme transmits data using lengthy sequences of scrambled data, separated by 8b/ 10b control character sequences that prepare the receiver for the next scrambled sequence and permit realignment if necessary. Several lanes are coded separately in this manner, and then multiplexed on a common channel. Alignment sequences in the control character sequences, as well as scrambler seeds, are set to avoid synchronization of patterns generated among all lanes, which would tend to confuse a receiving serdes and/or phase-locked loop that recovers timing from the multiplexed scrambled signals.

公开(公告)号：WO2003067906A2

公开(公告)日：2003-08-14

申请号：PCT/US2002/027999

申请日：2002-09-03

Applicant: FORCE10 NETWORKS, INC.

Inventor： GOERGEN, Joel, R.

IPC: H04Q1/10

CPC classification number: H05K1/0245 ,  H04Q1/03 ,  H04Q1/10 ,  H04Q1/155 ,  H04Q2201/12 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09354 ,  H05K2201/09636

Abstract: A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routing in a common backplane. Disclosed backplane features allow backplane signaling at 2.5 Gbps or greater on electrical differential pairs distributed on multiple high-speed signaling layers. Relatively thick power distribution layers are embedded within the backplane, shielded from the high-speed signaling layers by digital ground layers and other shielding features. A router using such a backplane provides a level of performance and economy that is believed to be unattainable by the prior art.

Abstract translation: 公开了一种高速，高功率模块化路由器。 与使用光学背板信号传输和/或母线进行配电的常规设计相反，所公开的实施例将高功率，低噪声功率分配与高速信号路由结合在公共背板中。 公开的背板功能允许在分布在多个高速信令层上的电气差分对上以2.5 Gbps或更高的背板信号传输。 相对较厚的配电层嵌入在背板内，通过数字接地层和其他屏蔽功能与高速信号层隔离。 使用这种背板的路由器提供了现有技术无法达到的性能和经济水平。

公开(公告)号：WO2012071423A1

公开(公告)日：2012-05-31

申请号：PCT/US2011/061864

申请日：2011-11-22

Applicant: FORCE10 NETWORKS, INC. ,  ZINJUWADIA, Kalpesh ,  RAO, Srikanth

Inventor： ZINJUWADIA, Kalpesh ,  RAO, Srikanth

IPC: H04J1/10

CPC classification number: H04L45/04 ,  H04L45/021 ,  H04L45/54 ,  H04L45/745

Abstract: A packet network device includes a route processor that operates to maintain one or more forwarding tables and it includes one or more line cards that operate to process information received by the packet network device from the network and to forward the information to its correct destination. The route processor also operates to identify which incoming prefixes can be used to update the forwarding tables or to identify prefixes stored in the packet network device that can be redistributed from one network protocol to another network protocol running on the route processor. A table management function running on the route processor operates to identify the best match between an incoming prefix and information included in policy statement associated with both an ordered prefix-list and a radix tree structure.

Abstract translation: 分组网络设备包括操作以维护一个或多个转发表的路由处理器，并且其包括一个或多个线卡，其操作以处理由分组网络设备从网络接收的信息，并将信息转发到其正确的目的地。 路由处理器还用于识别哪些入站前缀可用于更新转发表，或者识别存储在分组网络设备中的可以从一个网络协议重新分配到在路由处理器上运行的另一个网络协议的前缀。 在路由处理器上运行的表管理功能用于识别输入前缀和包括在与有序前缀列表和基数树结构相关联的策略语句中的信息之间的最佳匹配。

公开(公告)号：WO2009023238A1

公开(公告)日：2009-02-19

申请号：PCT/US2008009713

申请日：2008-08-13

Applicant: FORCE10 NETWORKS INC

Inventor： GOERGEN JOEL R ,  HUNT GREG

IPC: H05K3/42 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0216 ,  H05K1/0237 ,  H05K3/0047 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49165

Abstract: A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru- holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

Abstract translation: 公开了一种高速路由器背板。 路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。 通孔用于将差分信号对连接到外部组件。 为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。 钻出至少一些通孔和通孔以减少孔的导电短截线长度部分。 孔的钻孔部分包括从第一轮廓到第二轮廓的转变，以减少从钻孔的端部的射频反射。

公开(公告)号：WO03073808A8

公开(公告)日：2005-04-07

申请号：PCT/US0227987

申请日：2002-09-03

Applicant: FORCE10 NETWORKS INC

Inventor： GOERGEN JOEL R

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

公开(公告)号：US10320714B2

公开(公告)日：2019-06-11

申请号：US15246198

申请日：2016-08-24

Applicant: FORCE10 NETWORKS, INC

Inventor： Joel R. Goergen

IPC: H04L12/931 ,  H04L12/64 ,  H04W56/00 ,  H04W72/12 ,  H04W28/02 ,  H04W28/18

Abstract: A packet network device such as a network switch includes a number of functional cards or chassis modules at least some of which are connected to both an electrical backplane and a wireless backplane. The electrical backplane provides data plane signal paths and the wireless backplane provides control plane signal paths.

公开(公告)号：US09705824B2

公开(公告)日：2017-07-11

申请号：US14622267

申请日：2015-02-13

Applicant: Force10 Networks, Inc.

Inventor： David K. Wong

IPC: H04L12/403 ,  H04L12/931 ,  G08B21/18 ,  H04J3/04 ,  H04J3/24 ,  G06F15/16

CPC classification number: H04L49/40 ,  G06F15/161 ,  G08B21/18 ,  H04J3/047 ,  H04J3/247 ,  H04L12/403

Abstract: A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

公开(公告)号：US09509602B2

公开(公告)日：2016-11-29

申请号：US14181483

申请日：2014-02-14

Applicant: FORCE10 NETWORKS, INC

Inventor： Janardhanan P. Narasimhan ,  Krishnamurthy Subramanian ,  Thayumanavan Sridhar

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/931 ,  H04L12/947

CPC classification number: H04L45/74 ,  H04L49/25 ,  H04L49/351 ,  H04L49/70

Abstract: A LAN includes a CORE switch, some number of TOR switches, each linked to the CORE switch, and each of the TOR switches are linked directly to some number of host devices. Each of the switches in the LAN operate to process and transmit data frames they receive from neighboring LAN devices. Each TOR switch in the LAN builds and maintains a layer-2 forwarding table that is comprised of MAC address information learned from frames they receive from neighboring LAN devices. Selected ports/VLAN s on some or all of the TOR devices are designated to be CORE/switch facing ports (CFP) or host facing ports (HFP). Each of the CFPs are configured to only learn the MAC address in unicast frames it receives and each of the HFPs can be configured to learn the MAC address of both unicast and multicast data frames provided the destination MAC address included in the unicast frame is known.

Abstract translation: LAN包括CORE交换机，一些TOR交换机，每个都连接到CORE交换机，每个TOR交换机直接链接到一些主机设备。 LAN中的每个交换机操作以处理和发送从相邻LAN设备接收的数据帧。 LAN中的每个TOR开关构建并维护一个二层转发表，其包括从从相邻LAN设备接收的帧中学习的MAC地址信息。 某些或所有TOR设备上的所选端口/ VLAN被指定为CORE /交换机端口（CFP）或主机端口（HFP）。 每个CFP被配置为仅在所接收的单播帧中学习MAC地址，并且如果已知单播帧中包括的目的地MAC地址，则可以将每个HFP配置为学习单播和多播数据帧的MAC地址。