公开(公告)号：US06414347B1

公开(公告)日：2002-07-02

申请号：US09790011

申请日：2001-02-09

Applicant: Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

Inventor： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC: H01L2972

CPC classification number: H01L27/10864 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10841 ,  H01L29/66666 ,  H01L29/7827

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

Abstract translation: 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

公开(公告)号：US6133116A

公开(公告)日：2000-10-17

申请号：US328708

申请日：1999-06-09

Applicant: Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

Inventor： Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8238

CPC classification number: H01L27/10844 ,  H01L21/762 ,  H01L21/765 ,  H01L27/10805 ,  H01L27/10873

Abstract: Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.

Abstract translation: 通过在浅沟槽隔离（STI）中采用导电屏蔽，具有低掺杂衬底和有源宽度无关阈值电压的亚微米隔离间距DRAM的窄通道无效无效DRAM单元晶体管结构。 所得到的单元晶体管结构对通过STI的栅极和相邻存储节点结的寄生E场渗透是高度免疫的，并且将非常适合于Gbit规模DRAM技术。 导电屏蔽被负电压偏压，以便最小化衬底中的侧壁耗尽。

公开(公告)号：US5654928A

公开(公告)日：1997-08-05

申请号：US639261

申请日：1996-04-23

Applicant: Kyu-Chan Lee ,  Jai-Hoon Sim

Inventor： Kyu-Chan Lee ,  Jai-Hoon Sim

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A current sense amplifier for use in a semiconductor memory device having a pair of sub-I/O lines and a pair of I/O lines includes a first circuit leg having a first PMOS transistor in series with a second NMOS transistor. A second circuit leg has a third PMOS transistor in series with a fourth NMOS transistor. The gates of the PMOS transistors are each cross coupled to the drain of the other PMOS transistor. The gates of the NMOS transistor are each cross coupled to the source of the PMOS transistor in the other circuit leg. The source of each PMOS transistor comprises a sub-Input/Output line with an Input/Output line located between the transistors in each of the legs.

Abstract translation: 用于具有一对子I / O线和一对I / O线的半导体存储器件的电流检测放大器包括具有与第二NMOS晶体管串联的第一PMOS晶体管的第一电路支路。 第二电路支路具有与第四NMOS晶体管串联的第三PMOS晶体管。 PMOS晶体管的栅极各自交叉耦合到另一个PMOS晶体管的漏极。 NMOS晶体管的栅极分别与另一个电路支路中的PMOS晶体管的源极交叉耦合。 每个PMOS晶体管的源极包括一个子输入/输出线，其中输入/输出线位于每个支路中的晶体管之间。

公开(公告)号：US07541241B2

公开(公告)日：2009-06-02

申请号：US11298836

申请日：2005-12-12

Applicant: Jai Hoon Sim ,  Jih Wen Chou

Inventor： Jai Hoon Sim ,  Jih Wen Chou

IPC: H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/41783 ,  H01L29/66553 ,  H01L29/66621

Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

Abstract translation: 存储单元结构包括半导体衬底，位于半导体衬底上的两个堆叠结构，位于两个堆叠结构的侧壁上的两个导电间隔物，覆盖两个导电间隔物之间​​的半导体衬底的一部分的栅极氧化物层和栅极结构 至少位于栅极氧化物层上。 特别地，两个堆叠结构中的每一个包括第一氧化物块，导电块和第二氧化物块，并且两个导电间隔物位于两个堆叠结构的两个导电块的侧壁上。 两个导电间隔物优选由多晶硅制成，并且具有比第二氧化物块的底表面低的顶端。 此外，介电隔离物位于两个导电间隔物中的每一个上。

公开(公告)号：US20090057741A1

公开(公告)日：2009-03-05

申请号：US11896418

申请日：2007-08-31

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract translation: 提供了动态随机存取存储器（DRAM）单元及其制造方法。 DRAM单元包括单元晶体管和单元电容器。 电池电容器包括第一，第二和第三电介质层，以及第一，第二和第三电容器电极。 第一电介质层位于第一电容器电极上。 第二电容器电极位于第一电介质层的顶部。 第二电介质层位于第二电容器电极上。 第三电容器电极位于第二电介质层上并与漏极电连接。 第三电介质层位于第三电容器电极和栅极之间，用于将栅极与第三电容器电极隔离。

公开(公告)号：US5703475A

公开(公告)日：1997-12-30

申请号：US671145

申请日：1996-06-24

Applicant: Kyu-Chan Lee ,  Jai-Hoon Sim

Inventor： Kyu-Chan Lee ,  Jai-Hoon Sim

IPC: G11C11/413 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/16

CPC classification number: G05F3/242

Abstract: A reference voltage generator includes a pull-up stage which pulls a reference voltage signal rapidly up toward 1/2Vcc at power-up. The pull-up stage is controlled by a controller which has a comparator and control voltage generator which are disabled after the pull-up operation is terminated so as to reduce stand-by current consumption. The controller includes a pair of NAND gates cross connected as an RS flip-flop to turn on the pull-up stage at power up. A boost signal allows the flip-flop to enable the comparator and control voltage generator after the power supply has stabilized. When the reference voltage signal reaches 1/2Vcc, the comparator sets the flip flop which turns off the pull-up stage and disables the comparator and control voltage generator.

Abstract translation: 一个参考电压发生器包括一个上拉电平，它在上电时将参考电压信号快速上升至+ E，加1/2 + EE Vcc。 上拉级由控制器控制，控制器具有比较器和控制电压发生器，在上拉操作结束后禁止，以减少待机电流消耗。 控制器包括一对NAND门，它们作为RS触发器交叉连接，以在上电时接通上拉电平。 升压信号允许触发器在电源稳定后使能比较器和控制电压发生器。 当参考电压信号达到+ E，fra 1/2 + EE Vcc时，比较器设置关闭上拉电平的触发器，并禁止比较器和控制电压发生器。

公开(公告)号：US5656946A

公开(公告)日：1997-08-12

申请号：US590301

申请日：1996-01-23

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C11/407 ,  G11C5/14 ,  H03K17/16

CPC classification number: G11C5/143

Abstract: A voltage driving circuit for use in a semiconductor memory device. The voltage driving circuit includes a generator which generates a first voltage for an operating mode of the device, a generator which generates a second voltage for a standby mode, and a pair of switches connected between the voltage generators and an operating circuit, for selectively supplying the first and second voltages thereto. The first and second switches each have a control terminal, both of which are commonly coupled to a mode signal, for allowing external control of the voltage selection. The first and second voltages are preferably set relative to each other so as to reduce the subthreshold leakage current consumed by the semiconductor memory during a standby mode, while maintaining a desired operating speed during an operating mode.

Abstract translation: 一种用于半导体存储器件的电压驱动电路。 电压驱动电路包括产生用于器件工作模式的第一电压的发生器，产生用于待机模式的第二电压的发生器和连接在电压发生器和操作电路之间的一对开关，用于选择性地供电 第一和第二电压。 第一和第二开关各自具有控制端子，两者都通常耦合到模式信号，用于允许电压选择的外部控制。 优选地，第一和第二电压相对于彼此设置，以便在待机模式期间减少由半导体存储器消耗的亚阈值泄漏电流，同时在操作模式期间保持期望的操作速度。

公开(公告)号：US20110170336A1

公开(公告)日：2011-07-14

申请号：US12856481

申请日：2010-08-13

Applicant: Jai Hoon Sim

Inventor： Jai Hoon Sim

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.

Abstract translation: 本发明涉及具有4F2尺寸单元的DRAM器件及其制造方法。 DRAM装置包括在一个方向上彼此平行布置的多个字线，彼此平行并与字线交叉排列的多个位线，以及多个存储单元，具有晶体管和与源极端子电连接的电容器 的晶体管。 晶体管的栅极端子以位线方向填充两个相邻的存储单元之间的相关联的沟槽，并且经由插入在栅极端子和所述两个相邻存储器单元之间的栅极绝缘膜同时覆盖所述两个相邻存储单元的侧壁。 位或字线方向上的栅极端子之间的间隔比1F更远，F表示最小的处理尺寸。

公开(公告)号：US06441422B1

公开(公告)日：2002-08-27

申请号：US09706482

申请日：2000-11-03

Applicant: Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Jai-hoon Sim

Inventor： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Jai-hoon Sim

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L27/10867

Abstract: An ultra-scalable hybrid memory cell having a low junction leakage and a process of fabricating the same are provided. The ultra-scalable hybrid memory cell contains a conductive connection to the body region therefore avoiding isolation of the P-well due to cut-off by the buried strap outdiffusion region. The ultra-scalable hybrid memory cell avoids the above by using a shallower than normal isolation region that allows the P-well to remain connected to the body of the memory cell.

Abstract translation: 提供具有低结漏电的超可扩展混合存储器单元及其制造工艺。 超可扩展混合存储器单元包含与身体区域的导电连接，从而避免由于掩埋带外扩散区域而导致的P阱的隔离。 超可扩展混合存储器单元通过使用允许P阱保持连接到存储器单元的主体的比普通隔离区更浅的方式来避免上述情况。

公开(公告)号：US06440793B1

公开(公告)日：2002-08-27

申请号：US09757514

申请日：2001-01-10

Applicant: Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

Inventor： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC: H01L218242

CPC classification number: H01L27/10841 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.