公开(公告)号：US20120134195A1

公开(公告)日：2012-05-31

申请号：US13298196

申请日：2011-11-16

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C5/06 ,  H01L21/8239

CPC classification number: H01L27/10823 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891

Abstract: The present invention relates to a memory device having 4F2 size cells and a method for fabricating the same. The memory device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other, and plural memory cells having a transistor that fills a groove between two adjoining memory cells in a direction of the bit lines. A side wall between the two adjoining memory cells is simultaneously covered by an insulating film formed between the gate terminal and the two memory cells. The gate terminal is connected electrically to a word line, drain terminals of two adjoining memory cells are connected electrically to a bit line, and the gate and drain terminals are alternately arranged. One of the plural memory cells is buried in the substrate, and is electrically connected with a substrate or a well formed in the substrate.

Abstract translation: 本发明涉及具有4F2尺寸单元的存储器件及其制造方法。 存储器件包括在一个方向上彼此平行布置的多个字线，彼此平行布置的多个位线，以及具有晶体管的多个存储器单元，该晶体管沿位线的方向填充两个相邻的存储单元之间的沟槽。 两个相邻的存储单元之间的侧壁同时由形成在栅极端子和两个存储单元之间的绝缘膜覆盖。 栅极端子与字线电连接，两个相邻存储单元的漏极端子与位线电连接，栅极和漏极端子交替布置。 多个存储单元中的一个被埋在衬底中，并且与形成在衬底中的衬底或阱电连接。

公开(公告)号：US06329249B1

公开(公告)日：2001-12-11

申请号：US09333574

申请日：1999-06-15

Applicant: Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

Inventor： Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

IPC: H01L218234

CPC classification number: H01L27/10844 ,  H01L21/823462

Abstract: A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.

Abstract translation: 一种制造具有不同栅氧化层的半导体器件的方法。 根据有源面积尺寸控制氧化，使得氧化物在较宽的有源宽度（周边区域）上生长较薄，并且以较窄的有效宽度（电池阵列区域）厚厚地生长。 在具有不同有源区的半导体衬底上形成栅极图案。 形成栅极隔离物，然后进行活性尺寸依赖氧化工艺以使氧化物层彼此不同地生长。

公开(公告)号：US06214661B1

公开(公告)日：2001-04-10

申请号：US09489771

申请日：2000-01-21

Applicant: Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

Inventor： Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

IPC: H01L218242

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: a) preparing a bottom Pt electrode formation; b) subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; c) depositing a BSTO layer on said oxygen enriched Pt layer; d) depositing an upper Pt electrode layer on the BSTO layer; e) subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and f) depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止BSTO材料层的氧扩散，包括：a）制备底部Pt电极 b）使底Pt层电极形成氧气等离子体处理，在底Pt电极上形成富氧Pt层; c）在所述富氧Pt层上沉积BSTO层; d）将上Pt电极层沉积在 BSTO层; e）使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 以及）在配有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：US5946243A

公开(公告)日：1999-08-31

申请号：US85569

申请日：1998-05-27

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L21/8242 ,  G11C8/08 ,  G11C11/407 ,  G11C11/408 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: Driving circuits with active body pull-capability for inhibiting boost delay include main, subordinate and boosted signal lines and a first driver circuit electrically coupled to the main signal line, to drive the main signal line at a first potential (e.g., Vcc). A second driver circuit, electrically coupled to the boosted signal line, is also provided to drive the boosted signal line at a second potential (e.g., Vpp) greater than the first potential. A first field effect transistor is provided as a pull-up transistor which has a gate, drain and source electrically coupled to the main signal line, the boosted signal line and the subordinate signal line, respectively. To reduce body-bias effects which might inhibit the speed and pull-up capability of the pull-up transistor, a second field effect transistor is provided to actively pull-up the body (e.g., active region) of the pull-up transistor. This second field effect has a gate, drain and source electrically coupled to the main signal line (or boosted signal line), the boosted signal line and the body of the pull-up transistor, respectively. The second field effect transistor is designed to provide a pull-up function to the body of the pull-up transistor so that the magnitude of the reverse bias between an inversion layer channel (e.g., N-type) and the body region (e.g., P-type) of the pull-up transistor is reduced when the pull-up transistor is turned on to provide a voltage boost to the subordinate signal line. This reduction in the reverse bias results in a reduction of the body-bias effect and the increase in threshold voltage typically associated with the body-bias effect.

Abstract translation: 具有用于抑制升压延迟的具有主体拉动能力的驱动电路包括主，从属和升压的信号线，以及电耦合到主信号线的第一驱动电路，以以第一电位（例如，Vcc）驱动主信号线。 还提供电耦合到升压信号线的第二驱动器电路，以在大于第一电位的第二电位（例如Vpp）下驱动升压信号线。 第一场效应晶体管被提供为上拉晶体管，其具有电耦合到主信号线，升压信号线和从属信号线的栅极，漏极和源极。 为了减少可能抑制上拉晶体管的速度和上拉能力的体偏置效应，提供第二场效应晶体管以主动上拉上拉晶体管的主体（例如，有源区）。 该第二场效应具有分别与主信号线（或升压信号线），升压信号线和上拉晶体管的主体电耦合的栅极，漏极和源极。 第二场效应晶体管被设计为向上拉晶体管的主体提供上拉功能，使得反向层通道（例如，N型）与体区之间的反向偏置的大小（例如， 当上拉晶体管导通时，上拉晶体管的P型减小，以向下级信号线提供升压。 反向偏置的这种减少导致身体偏置效应的降低和通常与体偏置效应相关联的阈值电压的增加。

公开(公告)号：US5701268A

公开(公告)日：1997-12-23

申请号：US701892

申请日：1996-08-23

Applicant: Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

Inventor： Kyu-chan Lee ,  Sang-bo Lee ,  Jai-hoon Sim

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

CPC classification number: G11C7/06 ,  G11C11/4091

Abstract: Integrated circuit memory devices include at least first and second memory cells electrically coupled to respective first and second sense bit signal lines of a sense amplifier. The sense amplifier comprises a circuit for amplifying a difference in potential between the first and second sense bit signal lines by driving these lines to respective first and second different potentials. A driving circuit is also provided for simultaneously driving the first and second sense bit signal lines towards the first potential in response to application of a boost control signal. This driving circuit preferably comprises a first capacitor electrically connected in series between the boost control input and the first sense bit signal line and a second capacitor electrically connected in series between the boost control input and the second sense bit signal line. The boost control signal is established at the first potential to drive both the sense bit signal lines from different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) towards the first potential, prior to amplification of the difference in potential between the first and second sense bit signal lines by the sense amplifier. The present invention enables the sense amplifier to operate in an environment where the power supply voltage (e.g., VCC) is reduced and the different intermediate potentials (e.g., 1/2VCC+, 1/2VCC) to be amplified are initially established at potentials below the normal sensitivity of the sense amplifier.

Abstract translation: 集成电路存储器件包括电耦合到读出放大器的相应第一和第二感测位信号线的至少第一和第二存储器单元。 感测放大器包括用于通过将这些线驱动到相应的第一和第二不同电位来放大第一和第二感测位信号线之间的电位差的电路。 还提供驱动电路，用于响应于施加升压控制信号，同时将第一和第二感测位信号线驱动朝向第一电位。 该驱动电路优选地包括串联电连接在升压控制输入和第一感测位信号线之间的第一电容器和串联电连接在升压控制输入和第二感测位信号线之间的第二电容器。 升压控制信号被建立在第一电位，以驱动来自不同中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E，fra 1/2 + EE VCC）的感测位信号线朝着第一 在由感测放大器放大第一和第二感测位信号线之间的电位差之前的电位。 本发明使得读出放大器能够在电源电压（例如，VCC）减小的环境中工作，并且不同的中间电位（例如，+ E，fra 1/2 + EE VCC +，+ E， + EE VCC）最初建立在低于读出放大器正常灵敏度的电位。

公开(公告)号：US08872259B2

公开(公告)日：2014-10-28

申请号：US13445798

申请日：2012-04-12

Applicant: Seung Hwan Kim ,  Jai Hoon Sim

Inventor： Seung Hwan Kim ,  Jai Hoon Sim

IPC: H01L29/66 ,  H01L27/108 ,  H01L27/02

CPC classification number: H01L27/10823 ,  H01L27/0218 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/42364

Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

Abstract translation: 提供半导体器件及其制造方法，以防止浮体效应并降低掩埋位线之间的耦合电容。 半导体器件包括设置在半导体衬底上并包括垂直沟道区的第一柱，位于第一柱内部的垂直沟道区的下部的位线和从半导体衬底延伸至半导体衬底的一个侧壁的半导体层 第一支柱

公开(公告)号：US20130105872A1

公开(公告)日：2013-05-02

申请号：US13445798

申请日：2012-04-12

Applicant: Seung Hwan KIM ,  Jai Hoon Sim

Inventor： Seung Hwan KIM ,  Jai Hoon Sim

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/0218 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/42364

Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

公开(公告)号：US08084321B2

公开(公告)日：2011-12-27

申请号：US13151922

申请日：2011-06-02

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L21/8234

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

公开(公告)号：US20110230023A1

公开(公告)日：2011-09-22

申请号：US13151922

申请日：2011-06-02

Applicant: Jai-Hoon SIM

Inventor： Jai-Hoon SIM

IPC: H01L21/8242

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract translation: 提供了动态随机存取存储器（DRAM）单元及其制造方法。 DRAM单元包括单元晶体管和单元电容器。 电池电容器包括第一，第二和第三电介质层，以及第一，第二和第三电容器电极。 第一电介质层位于第一电容器电极上。 第二电容器电极位于第一电介质层的顶部。 第二电介质层位于第二电容器电极上。 第三电容器电极位于第二电介质层上并与漏极电连接。 第三电介质层位于第三电容器电极和栅极之间，用于将栅极与第三电容器电极隔离。

公开(公告)号：US20080057660A1

公开(公告)日：2008-03-06

申请号：US11511977

申请日：2006-08-29

Applicant: Kuo-Chi Tu ,  Jai-Hoon Sim ,  Chun-Yao Chen

Inventor： Kuo-Chi Tu ,  Jai-Hoon Sim ,  Chun-Yao Chen

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L27/10885 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/7835

Abstract: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.

Abstract translation: 一种使用凹陷步进栅极的半导体器件。 一个实施例包括在衬底的一部分中的凹陷区域，具有位于凹陷区域内的一个源极/漏极区域和位于凹陷区域外部的一个源极/漏极区域的晶体管，连接到源极/漏极的存储器件 以及连接到位于凹陷区域内的源极/漏极的位线。