-
公开(公告)号：US20040103266A1
公开(公告)日：2004-05-27
申请号：US10705946
申请日：2003-11-13
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/44
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.
Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定移位量的单个指令和包含多个数据元素的寄存器，其中所述执行单元可操作以移位每个 多个数据元素的移位量产生第二多个数据元素; 并且提供第二多个数据元素作为连接结果。
-
公开(公告)号：US10365926B2
公开(公告)日：2019-07-30
申请号：US15147811
申请日：2016-05-05
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
IPC: G06F9/30 , G06F9/38 , G06F9/35 , G06F9/455 , G06F12/02 , G06F17/50 , H03M13/15 , H03M13/41 , G06F9/448 , G06F9/44 , G03F1/36
Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path with of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
-
公开(公告)号：US20190065149A1
公开(公告)日：2019-02-28
申请号：US16150224
申请日：2018-10-02
Applicant: MicroUnity Systems Engineering, Inc.
Inventor： Craig Hansen , John Moussouris , Alexia Massalin
Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.
-
14.发明申请公开(公告)号：US20040210745A1
公开(公告)日：2004-10-21
申请号：US10757939
申请日：2004-01-16
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/00
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction that operates on a plurality of data elements in partitioned fields of at least one of the registers to produce a catenated result.
Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可配置为执行来自所述多个线程的多个指令流，其中每个指令流包括对分割字段中的多个数据元素进行操作的组指令 至少有一个寄存器产生连带结果。
-
公开(公告)号：US20040205325A1
公开(公告)日：2004-10-14
申请号：US10757866
申请日：2004-01-16
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/00
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.
Abstract translation: 一种用于通过结合执行单元的系统和软件，所述执行单元可操作以解码和执行指定掩模和包含数据的寄存器的单个指令，所述掩码包括各自对应于包含在所述寄存器中的数据的字段的字段， 所述执行单元可操作以将所述掩模的一些场检测为具有预定值，并将包含在所述寄存器中的数据的相应字段识别为可写入数据字段; 并使写入使能的数据字段被写入指定的存储器位置。
-
Patent Agency Ranking
16.发明申请公开(公告)号：US20040205324A1
公开(公告)日：2004-10-14
申请号：US10757851
申请日：2004-01-16
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/44
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.
Abstract translation: 一种用于通过并入执行单元的方法和软件，该执行单元可操作以解码和执行指定三个寄存器的单个指令，每个寄存器包含多个数据元素，所述执行单元可操作以将第一和第二寄存器相乘并将第三寄存器添加到 产生包含多个数据元素的连接结果。 附加指令提供组浮点减法，加，乘，少设置和设置更大的相等操作。 集合较少和设置较大相等的操作为连接结果的每个元素产生替代零或身份元素，结果便于使用逐位布尔运算而不需要条件分支操作来替代选择各个数据元素。
-
公开(公告)号：US20040153632A1
公开(公告)日：2004-08-05
申请号：US10757925
申请日：2004-01-16
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
Inventor： Craig Hansen , John Moussouris
IPC: G06F009/00
CPC classification number: G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30054 , G06F9/30087 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30123 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/3861 , G06F9/3873 , G06F9/3885 , G06F15/7832
Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
Abstract translation: 一种用于通过结合执行单元来提高处理器的性能的系统和软件，所述执行单元可操作以解码和执行指定数据选择操作数的单个指令，以及提供多个数据元素的第一和第二寄存器，所述数据选择操作数包括多个字段 每个选择所述多个数据元素中的一个，所述执行单元可操作以将所述数据选择操作数的每个字段所选择的数据元素提供到预定位置。
-
公开(公告)号：WO1996021968A1
公开(公告)日：1996-07-18
申请号：PCT/US1995012415
申请日：1995-09-29
Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.
IPC: H03D03/00
CPC classification number: H03D3/007 , H03D2200/005 , H03D2200/0052 , H03D2200/0062 , H03D2200/0072
Abstract: A digital FM demodulator and method for determining phase changes in highly oversampled complex FM digital signals is described. In a first embodiment the FM signal is oversampled with respect to the frequency of its associated modulating signal. In this embodiment a first digital processing stage delays and conjugates the original FM signal. This delayed conjugated original FM signal is then multiplied with the original FM signal to generate a second signal that represents the changes in the phase between samples of the original FM signal. A second processing stage then delays and conjugates the second signal. The delayed conjugated second signal is then multiplied with the original second signal to generate a third signal that represents changes in the phase between samples of the second signal. The imaginary component of the third signal is passed through a digital integrator which outputs the phase changes of the original FM signal. In a second embodiment, the highly oversampled signal is oversampled with respect to the deviation frequency of its associated modulating signal. In this embodiment the center frequency of the original FM signal is frequency shifted to approximately zero frequency. This frequency shifted signal is then delayed and conjugated. The delayed conjugated shifted signal is then multiplied with the original frequency shifted signal; yielding an output signal where the imaginary portion of the output signal is equal to the phase changes of the original FM signal.
Abstract translation: 描述了用于确定高度过采样的复数FM数字信号中的相位变化的数字FM解调器和方法。 在第一实施例中，FM信号相对于其相关调制信号的频率被过采样。 在该实施例中，第一数字处理级延迟并共轭原始FM信号。 然后将该延迟的共轭原始FM信号与原始FM信号相乘以产生表示原始FM信号的样本之间的相位变化的第二信号。 第二处理级然后延迟并共轭第二信号。 然后将延迟的共轭第二信号与原始第二信号相乘以产生表示第二信号的样本之间的相位变化的第三信号。 第三信号的虚分量通过数字积分器，该数字积分器输出原始FM信号的相位变化。 在第二实施例中，高度过采样的信号相对于其相关调制信号的偏差频率被过采样。 在这个实施例中，原始FM信号的中心频率被频移到大致零频率。 然后，该频移信号被延迟并共轭。 然后将延迟的共轭移位信号与原始频移信号相乘; 产生输出信号，其中输出信号的虚部等于原始FM信号的相位变化。
-
公开(公告)号：WO1996003807A1
公开(公告)日：1996-02-08
申请号：PCT/US1995009349
申请日：1995-07-25
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. , MOSTYN, Graham, Y. , HERNDON, William, H. , MOUSSOURIS, John, P. , ROBINSON, Timothy, B. , ROSSEEL, Geert, P.
Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.
IPC: H03K19/0185
CPC classification number: H03K19/0013 , H03K19/018507
Abstract: The present invention is an improvement of a digital topology including a logic block portion and a buffer portion. The improved buffer portion of the present invention is implemented with first and second parallel, same conductivity type transmission gates. The transmission gates couple either a first (V1) or second (V2) voltage onto the output of the buffer (55) in response to a logic signal originating from the logic block portion. The first (V1) and second (V2) voltages are selected to be relatively close in magnitude such that the peak-to-peak voltage of the digital output signal seen on the output of the buffer is relatively small. As a result, power consumption for charging the output of the buffer is minimized. In addition, the parallel transmission gates only consume power while charging the output of the buffer so that quiescent power consumption of the buffer is eliminated. Quiescent power dissipation is also eliminated in certain types of logic block designs that include logic gates having constant current sources. This is achieved by enabling the current sources with a pulse signal. The pulse width and magnitude of the pulse signal is selected to allow a latched sense amplifier to sense valid data from the output of the logic block portion during a specified interval. After valid data is sensed, the logic blocks's current sources are disabled, and the logic block portion no longer consumes any power. The sense amplifier is enabled for intervals long enough to capture the data from the logic block and drive the transmission gates with the data. In this configuration, none of the elements in the topology dissipate quiescent power since none of them are constantly operating.
Abstract translation: 本发明是包括逻辑块部分和缓冲部分的数字拓扑的改进。 本发明的改进的缓冲部分由第一和第二平行的相同导电类型的传输门来实现。 响应于源自逻辑块部分的逻辑信号，传输门将第一（V1）或第二（V2）电压耦合到缓冲器（55）的输出上。 第一（V1）和第二（V2）电压被选择为相对接近于幅度，使得在缓冲器的输出端上看到的数字输出信号的峰 - 峰电压相对较小。 结果，对缓冲器的输出进行充电的功耗最小化。 此外，并行传输门仅在缓冲器的输出充电时消耗功率，从而消除了缓冲器的静态功耗。 在包括具有恒定电流源的逻辑门的某些类型的逻辑块设计中也消除了静态功耗。 这是通过使能脉冲信号的电流源实现的。 选择脉冲信号的脉冲宽度和幅度以允许锁存的读出放大器在指定的间隔期间从逻辑块部分的输出检测有效数据。 在检测到有效数据之后，逻辑块的当前源被禁用，并且逻辑块部分不再消耗任何电力。 读出放大器使能间隔足够长的时间来捕获来自逻辑块的数据，并用数据驱动传输门。 在这种配置中，拓扑中的任何元件都不会消耗静态功耗，因为它们都不会持续运行。
-
公开(公告)号：WO1993014445A1
公开(公告)日：1993-07-22
申请号：PCT/US1993000456
申请日：1993-01-15
Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.
IPC: G03F09/00
CPC classification number: G03F1/36 , G03F7/70433 , G03F7/70441
Abstract: An improvement for reducing proximity effects comprised of additional lines, referred to as intensity leveling bars, into the mask pattern. The leveling bars perform the function of adjusting the edge intensity gradients of isolated edges in the mask pattern, to match the edge intensity gradients of densely packed edges. Leveling bars are placed parallel to isolated edges such that intensity gradient leveling occurs on all isolated edges of the mask pattern. In addition, the leveling bars are designed to have a width significantly less than the resolution of the exposure tool. Therefore, leveling bars that are present in the mask pattern produce resist patterns that completely developed away when a nominal exposure energy is utilized during exposure of photoresist.
-
-
-
-
-
-
-
-
-
Search Results
145
records
(took 0.046 seconds)
