公开(公告)号：JP5748164B2

公开(公告)日：2015-07-15

申请号：JP2013542036

申请日：2011-11-17

Applicant: レイディアント テクノロジーズ,インコーポレイテッド ,  RADIANT TECHNOLOGIES,INC.

Inventor： エヴァンズ,ジョセフ,ティー ,  ウォード,カルヴィン,ビー.

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657 ,  G11C27/005 ,  G11C11/2293

公开(公告)号：JP2013530482A

公开(公告)日：2013-07-25

申请号：JP2013514146

申请日：2010-06-11

Applicant: レイディアント テクノロジーズ,インコーポレイテッドRadiant Technologies,Inc.

Inventor： エヴァンズ，ジョセフ，テイト

IPC: G11C11/22

CPC classification number: G11C11/22 ,  G11C11/221

Abstract: 強誘電体キャパシタ、可変インピーダンス素子および導電性負荷を含むメモリセルが開示される。 第１および第２の分極状態を特徴とする強誘電体キャパシタは、制御端子と第１のスイッチ端子との間に接続される。 可変インピーダンス素子は、制御端子上の信号によって決定される、第１および第２のスイッチ端子間のインピーダンスを有する。 導電性負荷は、第１の電力端子と第１のスイッチ端子との間に接続される。 第２のスイッチ端子は、第２の電力端子に接続される。 電位差が、第１および第２の電力端子間に印加された場合に、第１のスイッチ端子上の電位は、強誘電体キャパシタの分極状態によって決定された方法で変化する。
【選択図】図１

公开(公告)号：JP2019531570A

公开(公告)日：2019-10-31

申请号：JP2019510821

申请日：2017-08-28

Applicant: レイディアント テクノロジーズ,インコーポレイテッド ,  RADIANT TECHNOLOGIES,INC.

Inventor： エヴァンス,ジョーゼフ,ティー.,ジュニア ,  ウォード,カルヴィン,ビー.

IPC: G11C11/22 ,  H01L27/11509 ,  G11C11/56

Abstract: 強誘電体メモリおよび強誘電体メモリを動作させる方法が開示される。強誘電体メモリは、最大残留電荷Q max によって特徴付けられる強誘電体キャパシタを有する強誘電体メモリセルを含む。書き込み回路は、強誘電体キャパシタに保存するための3つ以上の状態を有するデータ値を受信する。書き込み回路は、強誘電体キャパシタのQ max を測定し、強誘電体キャパシタに保存される、測定されたQ max の分数である電荷を決定し、分数は、データ値によって決定される。書き込み回路は、Q max の分数倍に等しい電荷を強誘電体キャパシタに保存させる。読み出し回路は、強誘電体キャパシタに保存された電荷を測定し、強誘電体キャパシタのQ max を測定し、かつ測定された電荷および測定されたQ max からデータ値を決定することにより、強誘電体キャパシタに保存された値を決定する。 【選択図】図4

公开(公告)号：US20170011789A1

公开(公告)日：2017-01-12

申请号：US15271145

申请日：2016-09-20

Applicant: Radiant Technologies, Inc. ,  Radiant Technologies, Inc.

Inventor： Joseph T. Evans, JR. ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract translation: 公开了一种存储单元和由该存储单元构成的存储器。 根据本发明的存储器包括铁电电容器，电荷源和读取电路。 电荷源接收要存储在铁电电容器中的数据值。 电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。 读取电路确定存储在铁电体电容器中的电荷。 数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。 存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

公开(公告)号：US20150016175A1

公开(公告)日：2015-01-15

申请号：US14498911

申请日：2014-09-26

Applicant: Radiant Technologies, Inc. ,  Radiant Technologies, Inc.

Inventor： Joseph T. Evans, JR. ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract translation: 公开了一种存储单元和由该存储单元构成的存储器。 根据本发明的存储器包括铁电电容器，电荷源和读取电路。 电荷源接收要存储在铁电电容器中的数据值。 电荷源将数据值转换为存储在铁电电容器中的剩余电荷，并使残留电荷存储在铁电体电容器中。 读取电路确定存储在铁电体电容器中的电荷。 数据值具有三个不同的可能状态，并且所确定的电荷具有多于三个确定的值。 存储器还包括使铁电电容器进入预定的已知参考偏振状态的复位电路。

公开(公告)号：WO2011155951A1

公开(公告)日：2011-12-15

申请号：PCT/US2010/038433

申请日：2010-06-11

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： EVANS, Joseph, Tate

IPC: G11C11/22 ,  G11C11/24 ,  G11C7/10

CPC classification number: G11C11/22 ,  G11C11/221

Abstract: A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor.

Abstract translation: 公开了一种包括铁电电容器，可变阻抗元件和导电负载的存储单元。 特征在于第一和第二极化状态的铁电电容器连接在控制端子和第一开关端子之间。 可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗。 导电负载连接在第一电源端子和第一开关端子之间。 第二开关端子连接到第二电源端子。 当在第一和第二电源端子之间施加电位差时，第一开关端子上的电位以由铁电体电容器的极化状态确定的方式变化。

公开(公告)号：WO2009151177A1

公开(公告)日：2009-12-17

申请号：PCT/KR2008/003800

申请日：2008-06-30

Applicant: RADIANT TECHNOLOGIES, INC. ,  SEOUL NATIONAL UNIVERSITY INDUSTRY FOUNDATION ,  JO, Daehyung ,  LEE, Jeongkeun ,  HAN, Jinyoung ,  KWON, Taekyoung ,  KIM, Tae Il ,  HA, Tae Joon

Inventor： JO, Daehyung ,  LEE, Jeongkeun ,  HAN, Jinyoung ,  KWON, Taekyoung ,  KIM, Tae Il ,  HA, Tae Joon

IPC: H04B7/26

CPC classification number: G01S5/08 ,  G01S5/0252

Abstract: A method and an apparatus for estimating a location of a terminal are provided. The method includes: receiving at least one base station signal from each of at least one base station; computing received signal information with respect to the received signal; and estimating the location of the terminal based on signal transmission direction information associated with the base station and the computed received signal information. The present invention can accurately estimate the location of the terminal based on directional information of base station signals.

Abstract translation: 提供了一种用于估计终端的位置的方法和装置。 该方法包括：从至少一个基站中的每一个接收至少一个基站信号; 计算关于接收信号的接收信号信息; 以及基于与所述基站相关联的信号传输方向信息和所计算的接收信号信息来估计所述终端的位置。 本发明可以基于基站信号的方向信息来准确估计终端的位置。

公开(公告)号：WO1997035339A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001880

申请日：1997-02-06

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T., Jr. ,  BOYER, Leonard, O.

IPC: H01L21/70

CPC classification number: H01L27/11502 ,  H01L28/55 ,  Y10S148/014

Abstract: A method for fabricating an integrated circuit having at least one integrated circuit component (14) fabricated in a silicon substrate (12) and a second device (30) that is to be fabricated on a silicon oxide layer (16) that covers the integrated circuit component (14). The integrated circuit component (14) has a terminal that is to be connected to a corresponding terminal on the second device (30). The second device (30) includes an electrode structure (35) in contact with a dielectric component that includes a layer (33) of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon (17) is deposited over the silicon oxide layer (16). The electrode structure (35) is then fabricated by depositing one or more layers over the boundary layer (17). The ferroelectric layer (33) is then deposited over the electrode structure (35) and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.

公开(公告)号：WO1995008187A1

公开(公告)日：1995-03-23

申请号：PCT/US1994008681

申请日：1994-07-28

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: H01L21/44

CPC classification number: H01L27/11502 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S257/915

Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. A capacitor (40) can be built over the source (34) of a transistor (32). Cell (30) is constructed by first constructing a CMOS transistor (32) having a drain (33), gate region consisting of gate oxide (35) and gate electrode (36), and source (34). The gate structures are insulated with a glass layer (37). A capacitor (40) is then constructed by depositing a bottom electrode (42) on source (34). A ceramic layer (43) is then deposited and sintered. Finally, the top electrode (41) is deposited. The resulting structure may be heated in the presence of oxygen to a temperature in excess of 800 DEG C without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.

Abstract translation: 一种通过铂导体将硅衬底连接到电气部件的方法。 可以在晶体管（32）的源极（34）上构建电容器（40）。 通过首先构造具有漏极（33），由栅极氧化物（35）和栅极电极（36）构成的栅极区域以及源极（34）的CMOS晶体管（32）构成单元（30）。 栅极结构与玻璃层（37）绝缘。 然后通过在源极（34）上沉积底部电极（42）来构造电容器（40）。 然后沉积陶瓷层（43）并烧结。 最后，沉积顶部电极（41）。 所得到的结构可以在氧的存在下加热到超过800℃的温度，而不会破坏硅衬底和连接到铂导体的组件之间的电连接。 本发明利用TiN或TiW缓冲层将铂导体连接到硅衬底。 缓冲层作为单晶沉积在硅衬底上。 然后将铂层沉积在缓冲层上。 与缓冲层接触的铂层的区域也是单晶。

公开(公告)号：AU4037300A

公开(公告)日：2000-10-16

申请号：AU4037300

申请日：2000-03-27

Applicant: RADIANT TECHNOLOGIES INC

Inventor： EVANS JOSEPH T JR

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/51

Abstract: A ferroelectric memory cell for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 DEG C. The dielectric layer is encapsulated in an oxygen impermeable material such that the encapsulating layer prevents oxygen from entering or leaving the dielectric layer. The memory also includes a hydrogen barrier layer that inhibits the flow of oxygen to the top and bottom electrodes when the memory cell is placed in a gaseous environment containing hydrogen. In one embodiment of the invention, a hydrogen absorbing layer is included. In the preferred embodiment of the present invention, the hydrogen barrier layer is constructed from a material that will also bind hydrogen ions.