公开(公告)号：WO1997035339A1

公开(公告)日：1997-09-25

申请号：PCT/US1997001880

申请日：1997-02-06

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T., Jr. ,  BOYER, Leonard, O.

IPC: H01L21/70

CPC classification number: H01L27/11502 ,  H01L28/55 ,  Y10S148/014

Abstract: A method for fabricating an integrated circuit having at least one integrated circuit component (14) fabricated in a silicon substrate (12) and a second device (30) that is to be fabricated on a silicon oxide layer (16) that covers the integrated circuit component (14). The integrated circuit component (14) has a terminal that is to be connected to a corresponding terminal on the second device (30). The second device (30) includes an electrode structure (35) in contact with a dielectric component that includes a layer (33) of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon (17) is deposited over the silicon oxide layer (16). The electrode structure (35) is then fabricated by depositing one or more layers over the boundary layer (17). The ferroelectric layer (33) is then deposited over the electrode structure (35) and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.

公开(公告)号：WO1995008187A1

公开(公告)日：1995-03-23

申请号：PCT/US1994008681

申请日：1994-07-28

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: H01L21/44

CPC classification number: H01L27/11502 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S257/915

Abstract: A method for connecting a silicon substrate to an electrical component via a platinum conductor. A capacitor (40) can be built over the source (34) of a transistor (32). Cell (30) is constructed by first constructing a CMOS transistor (32) having a drain (33), gate region consisting of gate oxide (35) and gate electrode (36), and source (34). The gate structures are insulated with a glass layer (37). A capacitor (40) is then constructed by depositing a bottom electrode (42) on source (34). A ceramic layer (43) is then deposited and sintered. Finally, the top electrode (41) is deposited. The resulting structure may be heated in the presence of oxygen to a temperature in excess of 800 DEG C without destroying the electrical connection between the silicon substrate and components connected to the platinum conductor. The present invention utilizes a TiN or TiW buffer layer to connect the platinum conductor to the silicon substrate. The buffer layer is deposited as a single crystal on the silicon substrate. The platinum layer is then deposited on the buffer layer. The region of the platinum layer in contact with the buffer layer is also a single crystal.

Abstract translation: 一种通过铂导体将硅衬底连接到电气部件的方法。 可以在晶体管（32）的源极（34）上构建电容器（40）。 通过首先构造具有漏极（33），由栅极氧化物（35）和栅极电极（36）构成的栅极区域以及源极（34）的CMOS晶体管（32）构成单元（30）。 栅极结构与玻璃层（37）绝缘。 然后通过在源极（34）上沉积底部电极（42）来构造电容器（40）。 然后沉积陶瓷层（43）并烧结。 最后，沉积顶部电极（41）。 所得到的结构可以在氧的存在下加热到超过800℃的温度，而不会破坏硅衬底和连接到铂导体的组件之间的电连接。 本发明利用TiN或TiW缓冲层将铂导体连接到硅衬底。 缓冲层作为单晶沉积在硅衬底上。 然后将铂层沉积在缓冲层上。 与缓冲层接触的铂层的区域也是单晶。

公开(公告)号：WO1998029902A1

公开(公告)日：1998-07-09

申请号：PCT/US1996020669

申请日：1996-12-27

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  SEAGER, Carleton, H. ,  EVANS, Joseph, Tate, Jr.

IPC: H01L21/477

CPC classification number: H01L28/60 ,  H01L21/76886 ,  H01L28/55

Abstract: A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers (18) are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer (18) to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer (18) to a temperature between 100 DEG C and 300 DEG C for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer (24).

Abstract translation: 当半导体器件制造期间氧化铟电阻层（18）经受高温退火步骤时，抵消所遇到的电阻率增加的方法。 该方法利用恢复退火步骤，其在高温退火步骤已经使电阻率增加之后将氧化铟层（18）返回到其原始电阻率。 回收退火包括将电阻层（18）加热至100℃至300℃的温度一段取决于退火温度的时间。 即使当氧化铟层被密封在电介质层（24）下时也观察到恢复。

公开(公告)号：WO1997027631A1

公开(公告)日：1997-07-31

申请号：PCT/US1997000863

申请日：1997-01-21

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T., Jr. ,  WOMACK, Richard

IPC: H01L29/68

CPC classification number: H01L27/11502 ,  G11C11/22 ,  G11C11/5657

Abstract: A high density non volatile ferroelectric-based memory (500) based on ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET (10). A memory using either the one or two bit storage cells includes a plurality of word storage cells (502) organized into a rectangular array including a plurality of columns and rows. Each of the single bit memory cells (101) includes a pass transistor (115) and a ferroelectric storage element (116). All of the gates of the ferroelectric storage elements transistors are connected to a common gate electrode (122), and all of the source electrodes are connected to a common source electrode (121). If the memory is built as a two bit storage cell (300), all of the common source electrodes in each of the columns are connected electrically to a column electrode (504) corresponding to that column and all of the pass gates in each of the rows that are connected electrically to a row electrode (503) corresponding to that row.

Abstract translation: 基于以两端写入模式操作的铁电FET的高密度非挥发性铁电存储器（500）。 存储字可以由基于铁电FET（10）的一个或两个位存储单元构成。 使用一个或两个位存储单元的存储器包括组织成包括多个列和行的矩形阵列的多个字存储单元（502）。 单个位存储单元（101）中的每一个包括通过晶体管（115）和铁电存储元件（116）。 铁电存储元件晶体管的所有栅极连接到公共栅电极（122），并且所有源电极连接到公共源电极（121）。 如果存储器被构建为两位存储单元（300），则每个列中的所有公共源电极电连接到对应于该列的列电极（504），并且在每个列中的所有通孔 与行对应的行电极（503）电连接的行。

公开(公告)号：WO1996029742A1

公开(公告)日：1996-09-26

申请号：PCT/US1996003128

申请日：1996-03-09

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  WARREN, William, L. ,  TUTTLE, Bruce, A.

IPC: H01L29/78

CPC classification number: H01L29/516 ,  G11C11/223

Abstract: An improved ferroelectric FET structure (10) in which the ferroelectric layer (14) is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer (16) having first and second contacts (18, 19) thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode (12) and a ferroelectric layer (14) which is sandwiched between the semiconductor layer (16) and the bottom electrode (12). The ferroelectric layer (14) is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentration between 1 % and 8 %.

Abstract translation: 改进的铁电FET结构（10），其中掺杂铁电层（14）以减少保留损耗。 根据本发明的铁电FET包括其上具有第一和第二触点（18,19）的半导体层（16），第一和第二触点彼此分离。 铁电FET还包括夹在半导体层（16）和底部电极（12）之间的底部电极（12）和铁电体层（14）。 铁电层（14）由化学组成ABO 3的钙钛矿结构构成，其中B位置包含第一和第二元素以及具有大于+4的氧化态足够浓度的掺杂剂元素，以阻止在 第一次和第二次接触时间。 铁电FET结构优选在A位置包含Pb。 第一和第二元素分别优选为Zr和Ti。 优选的B位掺杂剂是浓度在1％和8％之间的铌，钽和钨。

公开(公告)号：WO1994027871A1

公开(公告)日：1994-12-08

申请号：PCT/US1994005847

申请日：1994-05-26

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  SHEA, David, B.

IPC: B65D05/56

CPC classification number: B65D77/02 ,  B65D77/042 ,  B65D81/38 ,  B65D81/3853 ,  B65D81/3897

Abstract: A shipping container system comprises an inner liner (1) for insertion into an inner shipping container (15), for insertion into an outer shipping container (16). The inner liner (1) comprises a layer of single- or double-bubble radiant barrier material (13) within a sealed vinyl pouch (21). Between the outer container (6) and the inner container (5) there is furnished at least one spacer tray (3), for providing a partially-surrounding pocket of air in contact with the exterior surface of the inner container (5). During sealing of the pouch (21), a pocket of air is allowed to remain in its interior so that the radiant barrier material (13) floats within the sealed pouch (21). The pockets of air provided allow for maximization of the thermal insulating properties of the system due primarily to the thermal reflective property of the radiant barrier material. The vinyl construction of the pouch material provides a durable protective cover for the radiant barrier material.

Abstract translation: 运输容器系统包括用于插入内部运输容器（15）中的内衬（1），用于插入到外运输容器（16）中。 内衬垫（1）包括在密封的乙烯基袋（21）内的单层或双气泡辐射阻挡材料层（13）。 在外部容器（6）和内部容器（5）之间设置有至少一个间隔托盘（3），用于提供与内部容器（5）的外表面接触的部分环绕的空气袋。 在密封袋（21）期间，允许空气袋保持在其内部，使得辐射阻挡材料（13）浮在密封袋（21）内。 提供的空气袋允许主要由于辐射屏障材料的热反射性能而使系统的绝热性能最大化。 袋材料的乙烯基结构为辐射屏障材料提供耐用的保护罩。

公开(公告)号：WO1993018530A1

公开(公告)日：1993-09-16

申请号：PCT/US1993001469

申请日：1993-02-18

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen ,  MONTROSS, Carl, Elijah, Jr.

IPC: H01G04/10

CPC classification number: H01L28/55 ,  Y10T29/435

Abstract: An improved method for constructing integrated circuit structures in which a buffer SiO2 layer (203) is used to separate various components comprising ferroelectric materials (208) or platinum (202) is disclosed. The invention prevents interactions between the SiO2 buffer layer (203) and the ferroelectric materials (208). The invention also prevents the cracking in the SiO2 which is commonly observed when the SiO2 layer (203) is deposited directly over a platinum region (202) on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material (208) and which is also an electrical insulator to separate the SiO2 layer (203) from the ferroelectric material (208) and/or the platinum regions (202).

Abstract translation: 公开了一种用于构建集成电路结构的改进方法，其中使用缓冲层SiO 2层分离包含铁电材料或铂的各种组分。 本发明防止了SiO 2缓冲层与铁电材料之间的相互作用。 本发明还防止当SiO 2层直接沉积在电路表面上的铂区域上时通常观察到的SiO 2中的开裂。 本发明利用了相对于铁电材料基本上是惰性的材料的缓冲层，其也是用于将SiO 2层与铁电材料和/或铂区分离的电绝缘体。

公开(公告)号：WO1998005074A1

公开(公告)日：1998-02-05

申请号：PCT/US1997013082

申请日：1997-07-25

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T., Jr.

IPC: H01L29/76

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L29/516

Abstract: A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell (200) is designed to store the information at a temperature less than a first temperature. The memory cell (200) includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 degrees C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). One of the contacts typically includes a platinum electrode (210). The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.

Abstract translation: 一种用于存储信息的铁电存储单元（200）。 通过设定残留极化的方向，将信息存储在铁电介质层（213）的剩余极化中。 铁电存储单元（200）被设计为在小于第一温度的温度下存储信息。 存储单元（200）包括夹住介电层（213）的顶部和底部触点，该介电层包括具有大于第一温度且低于400℃的居里点的铁电材料。电介质层（213）被封装在 不透氧材料，使得封装层（221）防止氧气进入或离开电介质层（213）。 一个触点通常包括铂电极（210）。 另一个接触可以包括具有间隔开的电极的类似电极或半导体层。

公开(公告)号：WO1994025840A1

公开(公告)日：1994-11-10

申请号：PCT/US1994004882

申请日：1994-05-03

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  BULLINGTON, Jeff, Allen ,  EVANS, Joseph, Tate, Jr. ,  MONTROSS, Carl, Elijah, Jr.

IPC: G01J05/34

CPC classification number: H04N5/33

Abstract: The sensing array (10) detects an image by measuring the changes in the dielectric constant of individual capacitors in a rectangular array of capacitors (30-38). The present invention avoids the use of isolation transistors to eliminate the effects of other capacitors in the array when measuring the capacitance of a given capacitor in the array. During the measurement of any given capacitor in the array (10) the present invention maintains a zero potential difference across the capacitors that are not being measured, thereby eliminating any interference that might be caused by these capacitors.

Abstract translation: 感测阵列（10）通过测量矩形电容器阵列（30-38）中的各个电容器的介电常数的变化来检测图像。 本发明避免了在测量阵列中的给定电容器的电容时，使用隔离晶体管来消除阵列中的其它电容器的影响。 在阵列（10）中的任何给定的电容器的测量期间，本发明保持了未被测量的电容器之间的零电位差，从而消除了可能由这些电容器引起的任何干扰。

公开(公告)号：WO1993004543A1

公开(公告)日：1993-03-04

申请号：PCT/US1992006914

申请日：1992-08-17

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: H04J14/00

CPC classification number: H04J14/08 ,  H04J14/083

Abstract: Devices for converting digital data into a light pulse train and decoding such a pulse train are disclosed. The light pulse generating device (60) generates a train of light pulses having a pattern determined by a numerical value represented by a plurality of binary bits. The light pulse train generating device (60) stores the bits in a register (62). Each cell (63-65) of the register is connected to a light switching device (71-73) that will interrupt a first light beam in response to a light signal if the value stored in the cell is a logical one. If the value is a logical 0, the interruption will not occur. The decoding device (80) utilizes a plurality of light activated switches (84-86) to route individual pulses in the light pulse train to different photodetectors (87-89). The light activated switching devices avoid the delays inherent in electrically activated switching devices.