Abstract:
A method for fabricating an integrated circuit having at least one integrated circuit component (14) fabricated in a silicon substrate (12) and a second device (30) that is to be fabricated on a silicon oxide layer (16) that covers the integrated circuit component (14). The integrated circuit component (14) has a terminal that is to be connected to a corresponding terminal on the second device (30). The second device (30) includes an electrode structure (35) in contact with a dielectric component that includes a layer (33) of ferroelectric material. In the method of the present invention, a boundary layer comprising non-conducting polysilicon (17) is deposited over the silicon oxide layer (16). The electrode structure (35) is then fabricated by depositing one or more layers over the boundary layer (17). The ferroelectric layer (33) is then deposited over the electrode structure (35) and etched to provide the dielectric component. The boundary layer is then removed utilizing an etchant that etches silicon oxide much slower than polysilicon.
Abstract:
A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell (200) is designed to store the information at a temperature less than a first temperature. The memory cell (200) includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 degrees C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). One of the contacts typically includes a platinum electrode (210). The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.
Abstract:
A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Q max . A write circuit receives a data value having more than two states for storage in the ferroelectric capacitor. The write circuit measures Q max for the ferroelectric capacitor, determines a charge that is a fraction of the measured Q max to be stored in the ferroelectric capacitor, the fraction being determined by the data value. The write circuit causes a charge equal to the fraction times Q max to be stored in the ferroelectric capacitor. A read circuit determines a value stored in the ferroelectric capacitor by measuring a charge stored in the ferroelectric capacitor, measuring Q max for the ferroelectric capacitor, and determining the data value from the measured charge and the measured Q max .
Abstract:
A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell is designed to store the information at a temperature less than a first temperature. The memory cell includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 °C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). The memory also includes a hydrogen barrier layer (225) that inhibits the flow of oxygen to the top and bottom electrodes when the memory cell is placed in a gaseous environment containing hydrogen. In one embodiment of the invention, a hydrogen absorbing layer is included. In the preferred embodiment of the present invention, the hydrogen barrier layer (225) is constructed from a material that will also bind hydrogen ions.
Abstract:
A high density non volatile ferroelectric-based memory (500) based on ferroelectric FET operated in a two terminal write mode. Storage words may be constructed either from one or two bit storage cells based on a ferroelectric FET (10). A memory using either the one or two bit storage cells includes a plurality of word storage cells (502) organized into a rectangular array including a plurality of columns and rows. Each of the single bit memory cells (101) includes a pass transistor (115) and a ferroelectric storage element (116). All of the gates of the ferroelectric storage elements transistors are connected to a common gate electrode (122), and all of the source electrodes are connected to a common source electrode (121). If the memory is built as a two bit storage cell (300), all of the common source electrodes in each of the columns are connected electrically to a column electrode (504) corresponding to that column and all of the pass gates in each of the rows that are connected electrically to a row electrode (503) corresponding to that row.
Abstract:
A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell (200) is designed to store the information at a temperature less than a first temperature. The memory cell (200) includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 degrees C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). One of the contacts typically includes a platinum electrode (210). The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.