公开(公告)号：WO2012002994A1

公开(公告)日：2012-01-05

申请号：PCT/US2011/001116

申请日：2011-06-23

Applicant: MATHESON TRI-GAS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FRANCIS, Terry, Arthur ,  HASAKA, Satoshi ,  BRABANT, Paul, David ,  TORRES, Robert, Jr. ,  HE, Hong ,  REZNICEK, Alexander ,  ADAM, Thomas, N. ,  SADANA, Devendra, K.

Inventor： FRANCIS, Terry, Arthur ,  HASAKA, Satoshi ,  BRABANT, Paul, David ,  TORRES, Robert, Jr. ,  HE, Hong ,  REZNICEK, Alexander ,  ADAM, Thomas, N. ,  SADANA, Devendra, K.

IPC: C30B25/02

CPC classification number: H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

Abstract: The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550°C and a pressure in the range of about 10 mTorr - 200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.

Abstract translation: 本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速 小于约550℃，压力范围为约10mTorr-200Torr。 此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳 。

公开(公告)号：WO2011106203A2

公开(公告)日：2011-09-01

申请号：PCT/US2011/024948

申请日：2011-02-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W ,  FOGEL, Keith, E ,  LAURO, Paul, A ,  SADANA, Devendra ,  SHAHRJERDI, Davood

Inventor： BEDELL, Stephen, W ,  FOGEL, Keith, E ,  LAURO, Paul, A ,  SADANA, Devendra ,  SHAHRJERDI, Davood

IPC: H01L21/304 ,  B28D5/00

CPC classification number: H01L31/075 ,  H01L21/02002 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

Abstract: A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture.

Abstract translation: 从半导体衬底的锭剥落层的方法包括在半导体衬底的锭上形成金属层，其中金属层中的拉伸应力构造成在晶锭中引起断裂; 并在断裂处从锭中去除层。 用于从半导体衬底的锭剥落层的系统包括形成在半导体衬底的锭上的金属层，其中金属层中的拉伸应力被配置为引起锭中的断裂，并且其中该层被配置 在断裂处从锭中移除。

公开(公告)号：WO2011104096A1

公开(公告)日：2011-09-01

申请号：PCT/EP2011/051545

申请日：2011-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  SOSA CORTES, Norma ,  BEDELL, Stephen ,  SHAHRJERDI, Davood ,  SADANA, Devendra ,  FOGEL, Keith

Inventor： SOSA CORTES, Norma ,  BEDELL, Stephen ,  SHAHRJERDI, Davood ,  SADANA, Devendra ,  FOGEL, Keith

IPC: H01L31/068 ,  H01L21/762 ,  H01L21/78

CPC classification number: H01L31/068 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548

Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.

Abstract translation: 制造多结光伏（PV）电池的方法包括在衬底上提供包括多个结的堆叠，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最小带隙的结点排序 位于具有最大带隙位于堆叠顶部的基底上的基底上; 在具有最大带隙的结的顶部上形成顶部金属层，顶部金属层具有拉伸应力; 将顶部柔性基底粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于顶部金属层中的拉伸应力形成断裂。

公开(公告)号：WO2007130333A3

公开(公告)日：2007-11-15

申请号：PCT/US2007/010411

申请日：2007-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W. ,  DESOUZA, Joel, P. ,  REN, Zhibin ,  REZNICEK, Alexander ,  SADANA, Devendra, K. ,  SAENGER, Katherine, L. ,  SHAHIDI, Ghavam

Inventor： BEDELL, Stephen, W. ,  DESOUZA, Joel, P. ,  REN, Zhibin ,  REZNICEK, Alexander ,  SADANA, Devendra, K. ,  SAENGER, Katherine, L. ,  SHAHIDI, Ghavam

IPC: H01L21/8234 ,  H01L21/336

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：WO2012118577A1

公开(公告)日：2012-09-07

申请号：PCT/US2012/022708

申请日：2012-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GUNAWAN, Oki ,  KIM, Jeehwan ,  MITZI, David, B. ,  SADANA, Devendra, K. ,  TODOROV, Teodor, K.

Inventor： GUNAWAN, Oki ,  KIM, Jeehwan ,  MITZI, David, B. ,  SADANA, Devendra, K. ,  TODOROV, Teodor, K.

IPC: H01L31/0256

CPC classification number: H01L31/0326 ,  C23C14/34 ,  C25D7/12 ,  H01L31/076 ,  H01L31/078 ,  H01L31/18 ,  H01L31/20 ,  Y02E10/548

Abstract: A photosensitive device and method includes a top cell (102) having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell (104) includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu-Zn-Sn containing chalcogenide (116).

Abstract translation: 感光装置和方法包括具有N型层的顶层单元（102），P型层和其间的顶层本征层。 底部单元（104）包括N型层，P型层和底层本征层。 底部本征层包括含有Cu-Zn-Sn的硫族化物（116）。

公开(公告)号：WO2011095473A1

公开(公告)日：2011-08-11

申请号：PCT/EP2011/051372

申请日：2011-02-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  BEDELL, Stephen ,  KIM, Jee, Hwan ,  INNS, Daniel ,  SADANA, Devendra ,  FOGEL, Keith ,  VICHICONTI, James

Inventor： BEDELL, Stephen ,  KIM, Jee, Hwan ,  INNS, Daniel ,  SADANA, Devendra ,  FOGEL, Keith ,  VICHICONTI, James

IPC: H01L21/18

CPC classification number: H01L21/187

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped Si Ge layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron- doped SiGe layer is configured to propagate a fracture at an interface between the boron- doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

Abstract translation: 使用硼掺杂硅锗（SiGe）层进行层转移的方法包括在体硅衬底上形成硼掺杂的SiGe层; 在掺杂硼的SiGe层上形成上硅（Si）层; 氢化硼掺杂的SiGe层; 将上部Si层结合到替代的基底上; 并在硼掺杂的SiGe层和体硅衬底之间的界面处传播断裂。 使用硼掺杂硅锗（SiGe）层的层转移系统包括体硅衬底; 形成在本体硅衬底上的硼掺杂Si Ge层，使得掺杂硼的SiGe层位于上硅（Si）层下方，其中掺硼的SiGe层被构造成在 硼掺杂SiGe层氢化后的硼掺杂SiGe层和体硅衬底; 以及与上部Si层接合的替代基板。

公开(公告)号：WO2011005447A2

公开(公告)日：2011-01-13

申请号：PCT/US2010039007

申请日：2010-06-17

Applicant: IBM ,  DE SOUZA JOEL ,  HOVEL HAROLD ,  INNS DANIEL ,  KIM JEE ,  SADANA DEVENDRA

Inventor： DE SOUZA JOEL ,  HOVEL HAROLD ,  INNS DANIEL ,  KIM JEE ,  SADANA DEVENDRA

IPC: H01L31/18 ,  H01L31/068 ,  H01L31/072 ,  H01L31/078

CPC classification number: H01L31/1872 ,  H01L31/03921 ,  H01L31/068 ,  H01L31/078 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A semiconductor is disclosed with a substrate doped with a substrate doping. There is a crystalline semiconductor layer disposed on a front side of the substrate. The crystalline semiconductor layer has a layer doping. The substrate doping changes to the layer doping within a 100 angstrom transition region. In alternative embodiments, the layer doping has novel profiles. In other alternative embodiments, the substrate has a crystalline semiconductor layers disposed on each of a front and a back side of the substrate. Each of the crystalline semiconductor layers has a respective layer doping and each of these layer dopings changes to the substrate doping within a respective transition region less than 100 angstroms thick. In still other embodiments of this invention, an amorphous silicon layer is disposed on a side of the crystalline semiconductor layer opposite the substrate. The amorphous silicon layer has an amorphous doping so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer. Manufacturing these structures at below 700 degrees Centigrade enables the narrow transition regions of the structures.

Abstract translation: 公开了一种掺杂有衬底掺杂的衬底的半导体。 在衬底的正面上设置有晶体半导体层。 晶体半导体层具有层掺杂。 衬底掺杂改变为在100埃过渡区内的层掺杂。 在替代实施例中，层掺杂具有新颖的轮廓。 在其他替代实施例中，衬底具有布置在衬底的前侧和后侧中的每一个上的晶体半导体层。 每个晶体半导体层具有相应的层掺杂并且这些层掺杂中的每一个都变为在小于100埃厚的相应过渡区域内的衬底掺杂。 在本发明的其他实施例中，非晶硅层设置在与衬底相对的晶体半导体层的一侧。 非晶硅层具有非晶掺杂，使得在掺杂的晶体半导体层和非晶层之间形成隧道结。 在700摄氏度以下制造这些结构使得结构的狭窄过渡区域成为可能。

公开(公告)号：WO2010151478A1

公开(公告)日：2010-12-29

申请号：PCT/US2010/039008

申请日：2010-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DE SOUZA, Joel ,  HOVEL, Harold ,  INNS, Daniel ,  KIM, Jee ,  SADANA, Devendra

Inventor： DE SOUZA, Joel ,  HOVEL, Harold ,  INNS, Daniel ,  KIM, Jee ,  SADANA, Devendra

IPC: H01L31/102

CPC classification number: H01L31/1872 ,  H01L31/03921 ,  H01L31/068 ,  H01L31/078 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of making a semiconductor structure is disclosed that deposits a front amorphous semiconductor layer on a front side of a semiconductor substrate and crystallizes the front amorphous semiconductor layer into a front doped crystalline semiconductor layer by applying heat within a low thermal budget temperature. In an alternative embodiment, a back doped crystalline semiconductor layer is added on a back side of the semiconductor substrate in the same way. Preferably the thermal budget temperature is below 700 degrees Centigrade. Alternatively, the thermal budget temperature is a rapid thermal processing temperature where the temperature is less than 900 degrees Centigrade and the time of temperature application is short to keep the thermal budget low. A method of making a tandem structure is also disclosed.

Abstract translation: 公开了一种制造半导体结构的方法，其通过在低热预算温度下施加热量将前非晶半导体层沉积在半导体衬底的正面上并将前非晶硅半导体层结晶成为前掺杂晶体半导体层。 在替代实施例中，以相同的方式将背掺杂晶体半导体层添加到半导体衬底的背面。 优选地，热预算温度低于700摄氏度。 或者，热预算温度是温度低于900摄氏度的快速热处理温度，并且温度施加的时间短以保持热量预算较低。 还公开了制作串联结构的方法。

公开(公告)号：WO2009056478A3

公开(公告)日：2009-05-07

申请号：PCT/EP2008/064272

申请日：2008-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen ,  DE SOUZA, Joel ,  REZNICEK, Alexander ,  SADANA, Devendra

Inventor： BEDELL, Stephen ,  DE SOUZA, Joel ,  REZNICEK, Alexander ,  SADANA, Devendra

IPC: H01L21/762

Abstract: A method of fabricating a strained semiconductor-on- insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.