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    DIE MODULE SYSTEM AND METHOD
    11.
    发明申请
    DIE MODULE SYSTEM AND METHOD 审中-公开

    公开(公告)号：WO2007001505A3

    公开(公告)日：2007-01-04

    申请号：PCT/US2006/006935

    申请日：2006-02-27

    Applicant: STAKTEK GROUP L.P. ,  CADY, James, W. ,  GOODWIN, Paul

    Inventor： CADY, James, W. ,  GOODWIN, Paul

    IPC: H05K1/11 ,  H01K1/14

    Abstract: A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.

    CIRCUIT MODULE WITH THERMAL CASING SYSTEMS AND METHODS
    12.
    发明申请
    CIRCUIT MODULE WITH THERMAL CASING SYSTEMS AND METHODS 审中-公开
    具有热壳系统和方法的电路模块

    公开(公告)号：WO2006121487A2

    公开(公告)日：2006-11-16

    申请号：PCT/US2006/007004

    申请日：2006-02-28

    Applicant: STAKTEK GROUP L.P. ,  WEHRLY, James, Douglas, Jr. ,  WILDER, James ,  WOLFE, Mark ,  GOODWIN, Paul

    Inventor： WEHRLY, James, Douglas, Jr. ,  WILDER, James ,  WOLFE, Mark ,  GOODWIN, Paul

    IPC: G06F11/00

    CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

    Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

    Abstract translation: 灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 填充的柔性电路围绕刚性衬底的边缘设置，优选地由导热材料设计，并且一个或多个散热器布置成与模块的组成集成电路中的至少一些热接触。 可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。 在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的放大表面。

    HIGH CAPACITY THIN MODULE SYSTEM AND METHOD
    13.
    发明申请
    HIGH CAPACITY THIN MODULE SYSTEM AND METHOD 审中-公开
    高容量薄模块系统和方法

    公开(公告)号：WO2006121486A2

    公开(公告)日：2006-11-16

    申请号：PCT/US2006/006921

    申请日：2006-02-28

    Applicant: STAKTEK GROUP L.P. ,  WEHRLY, JR, James Douglas ,  WILDER, James ,  GOODWIN, Paul ,  WOLFE, Mark

    Inventor： WEHRLY, JR, James Douglas ,  WILDER, James ,  GOODWIN, Paul ,  WOLFE, Mark

    IPC: G06F11/00

    CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

    Abstract: Flexible circuitry is populated with integrated circuitry disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. The circuit-populated flexible circuitry is disposed about an edge of a rigid substrate preferably devised from thermally conductive materials and includes a high thermal conductivity core or area that is disposed proximal to higher thermal energy devices such as an AMB when the flex circuit is brought about the substrate. Other variations include thermally-conductive clips that grasp respective ICs on opposite sides of the module to further shunt heat from the ICs. Preferred extensions from the substrate body or substrate core encourage reduced thermal variations amongst the integrated circuits of the module.

    Abstract translation: 灵活的电路装有集成电路，沿其主要一侧或两侧布置。 沿柔性电路分布的触点提供模块与应用环境之间的连接。 电路填充的柔性电路围绕刚性衬底的边缘设置，优选地由导热材料设计，并且包括当柔性电路产生时设置在较高热能装置（例如AMB）附近的高导热性芯或区域 底物。 其他变型包括将模块的相对侧上的相应IC夹持的导热夹子，以进一步从IC分流热量。 来自衬底主体或衬底芯的优选延伸部件促进模块集成电路之间的热变化减小。

    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD
    14.
    发明申请
    STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD 审中-公开
    堆叠集成电路CASCADE信号系统与方法

    公开(公告)号：WO2006028693A2

    公开(公告)日：2006-03-16

    申请号：PCT/US2005/029867

    申请日：2005-08-23

    Applicant: STAKTEK GROUP L.P. ,  CADY, James ,  RAPPORT, Russell ,  WILDER, James

    Inventor： CADY, James ,  RAPPORT, Russell ,  WILDER, James

    IPC: H01L23/02

    CPC classification number: H01L25/105 ,  H01L23/4985 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

    Abstract translation: 集成电路（IC）堆叠成可以节省PCB或其他板表面积的模块。 这些模块提供了较低电容存储器信号系统和用于以串联级联布置连接堆叠CSP的方法。 在一个优选实施例中，选择性地使用管芯端子来终止级联的导电路径。 在另一个优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在宽范围的CSP封装系列中发现许多变化的封装尺寸。

    Low profile chip scale stacking system and method
    17.
    发明申请
    Low profile chip scale stacking system and method 有权
    薄型芯片级堆叠系统及方法

    公开(公告)号：US20040229402A1

    公开(公告)日：2004-11-18

    申请号：US10873847

    申请日：2004-06-22

    Applicant: Staktek Group, L.P.

    Inventor： James W. Cady ,  Julian Partridge ,  James Douglas Wehrly JR. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

    IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/02

    CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。 薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。 薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。 提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以表现出一个或两个或更多个导电层。 在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如 ，柔性电路作为热转移材料。

    Low profile chip scale stacking system and method
    18.
    发明申请
    Low profile chip scale stacking system and method 失效
    薄型芯片级堆叠系统及方法

    公开(公告)号：US20040052060A1

    公开(公告)日：2004-03-18

    申请号：US10631886

    申请日：2003-07-14

    Applicant: Staktek Group, L.P.

    Inventor： James W. Cady ,  Julian Partridge ,  James Douglas Wehrly JR. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

    IPC: H05K001/00

    CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/49144

    Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile structures provide connection between CSPs of the stacked module and between and to the flex circuitry. Low profile contacts are created by any of a variety of methods and materials including, for example, screen paste techniques and use of high temperature solders, although other application techniques and traditional solders may be employed for creating low profile contacts in the present invention. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers. In some preferred embodiments, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In other embodiments, a heat spreader is disposed between the CSP and the flex circuitry thus providing an improved heat transference function without the standardization of the form standard, while still other embodiments lack either a form standard or a heat spreader and may employ, for example, the flex circuitry as a heat transference material.

    Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保留PWB或其他板表面积的低轮廓模块。 薄型结构提供堆叠模块的CSP之间和柔性电路之间的连接。 薄型触点由各种方法和材料中的任何一种产生，包括例如丝网糊技术和高温焊料的使用，尽管其它应用技术和传统焊料可用于在本发明中制造低轮廓触点。 提供了一种合并的低轮廓接触结构和技术，用于本发明的替代实施例。 根据本发明可以堆叠多个CSP。 根据本发明设计的堆叠模块中采用的CSP与柔性电路连接。 该柔性电路可以表现出一个或两个或更多个导电层。 在一些优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在广泛的CSP封装系列中发现许多变化的封装尺寸。 在其他实施例中，散热器设置在CSP和柔性电路之间，从而提供改进的热传递功能，而不需要形式标准的标准化，而其它实施例还没有形式标准或散热器，并且可以采用例如 ，柔性电路作为热转移材料。

    Stacking system and method
    20.
    发明申请
    Stacking system and method 审中-公开
    堆叠系统和方法

    公开(公告)号：US20030137048A1

    公开(公告)日：2003-07-24

    申请号：US10400309

    申请日：2003-03-27

    Applicant: Staktek Group, L.P.

    Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly JR. ,  Julian Dowden ,  Jeff Buchle

    IPC: H01L023/14

    CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

    Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。 两个集成电路与一对柔性电路结构连接。 一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。 柔性电路对连接上下集成电路，并且在模块与诸如印刷电路板（PWB）的应用环境之间提供热和电路连接路径。 本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

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