中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.041 seconds)

    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION
    11.
    发明申请
    THROUGH SILICON VIA LITHOGRAPHIC ALIGNMENT AND REGISTRATION 审中-公开
    通过光刻对齐和注册来实现硅通孔

    公开(公告)号：WO2011090852A2

    公开(公告)日：2011-07-28

    申请号：PCT/US2011020913

    申请日：2011-01-12

    Applicant: IBM ,  HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    Inventor： HERRIN RUSSELL T ,  LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate (100; Figure 1) and lines the first opening with a protective liner. (102) The method deposits a material into the first opening (104) and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. (108) The method removes the material from the first opening through the second opening in the protective material. (110) The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

    Abstract translation: 制造集成电路结构的方法在衬底（100;图1）中形成第一开口并用保护性衬垫排列第一开口。 （102）该方法将材料沉积到第一开口（104）中并且在衬底上形成保护材料。 保护材料包括过程控制标记并且包括在第一开口上方并与第一开口对齐的第二开口。 （108）该方法通过保护材料中的第二开口从第一开口移除材料。 （110）过程控制标记包括保护材料内的凹部，其仅部分地延伸穿过保护材料，使得过程控制标记下方的部分基板不受移除材料的过程的影响。

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    12.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    在混合方向晶体管中对充电损害的保护

    公开(公告)号：WO2007115146A2

    公开(公告)日：2007-10-11

    申请号：PCT/US2007/065604

    申请日：2007-03-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HOOK, Terence, B. ,  MOCUTA, Anda, C. ,  SLEIGHT, Jeffrey, W. ,  STAMPER, Anthony, K.

    Inventor： HOOK, Terence, B. ,  MOCUTA, Anda, C. ,  SLEIGHT, Jeffrey, W. ,  STAMPER, Anthony, K.

    IPC: A61K31/203 ,  A61K9/127

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下伏体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）设置在通过掩埋介电层（16）与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES
    13.
    发明申请
    CMOS IMAGER OF ELIMINATING HIGH REFLECTIVITY INTERFACES 审中-公开
    消除高反射性界面的CMOS图像

    公开(公告)号：WO2006071540A3

    公开(公告)日：2007-04-12

    申请号：PCT/US2005045328

    申请日：2005-12-14

    Applicant: IBM ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  RASSEL RICHARD J ,  STAMPER ANTHONY K

    IPC: H01L29/04

    CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    Abstract: An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: 一种图像传感器（20）及其制造方法，其中传感器包括铜（Cu）金属化水平（135a，135b），允许结合更薄的层间电介质堆叠（130a-130c）以产生呈现增加的像素阵列（100） 光敏感。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属（132a，132b）的最小厚度的结构，或者具有从每个的光路中选择性地去除的阻挡层金属的部分（50） 像素，从而最小化反射率。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层（142）可以通过自对准沉积形成在Cu金属化之上。

    METHOD AND FORMING A SEMICONDUCTOR DEVICE HAVING AIR GAPS AND THE STRUCTURE SO FORMED
    14.
    发明申请
    METHOD AND FORMING A SEMICONDUCTOR DEVICE HAVING AIR GAPS AND THE STRUCTURE SO FORMED 审中-公开
    方法和形成具有空气GAPS和形成的结构的半导体器件

    公开(公告)号：WO2005117085A2

    公开(公告)日：2005-12-08

    申请号：PCT/US2005/018050

    申请日：2005-05-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION? ,  STAMPER, Anthony, K.

    Inventor： STAMPER, Anthony, K.

    IPC: H01L21/311

    CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

    Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first dielectric material (12a-f) and a second dielectric material (14a-f), wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature (22, 24) within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion (26) of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

    Abstract translation: 形成半导体器件的方法和如此形成的器件。 沉积第一介电材料（12a-f）和第二介电材料（14a-f）的交替层，其中所述第一和第二介电材料可以以不同的速率被选择性地蚀刻。 在电介质材料的交替层内形成第一特征（22,24）。 选择性地蚀刻介电材料的交替层以去除具有第一介电材料的每个层中的第一介电材料的至少一部分（26），并使第二介电材料基本上未被蚀刻。

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    20.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    在混合方向晶体管中对充电损害的保护

    公开(公告)号：WO2007115146B1

    公开(公告)日：2008-06-05

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

Patent Agency Ranking