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    METHOD OF MANUFACTURING ELECTRONIC DEVICES AND CORRESPONDING ELECTRONIC DEVICE
    14.
    发明申请
    METHOD OF MANUFACTURING ELECTRONIC DEVICES AND CORRESPONDING ELECTRONIC DEVICE 有权

    公开(公告)号：US20230110259A1

    公开(公告)日：2023-04-13

    申请号：US18079704

    申请日：2022-12-12

    Applicant: STMicroelectronics (MALTA) Ltd ,  STMicroelectronics S.r.l.

    Inventor： Kevin FORMOSA ,  Marco DEL SARTO

    IPC: B81C1/00 ,  B81B7/00

    Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.

    INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE
    15.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE 有权

    公开(公告)号：US20230046645A1

    公开(公告)日：2023-02-16

    申请号：US17870235

    申请日：2022-07-21

    Applicant: STMicroelectronics (Malta) Ltd.

    Inventor： Roseanne DUCA

    IPC: H01L23/498 ,  H01L23/00 ,  B81B7/00

    Abstract: A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.

    SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD 有权

    公开(公告)号：US20230005755A1

    公开(公告)日：2023-01-05

    申请号：US17942843

    申请日：2022-09-12

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (MALTA) Ltd

    Inventor： Roseanne DUCA ,  Dario PACI ,  Pierpaolo RECANATINI

    IPC: H01L21/324 ,  H01L23/16 ,  H01L23/31

    Abstract: A leadframe includes a die pad and a set of electrically conductive leads. A semiconductor die, having a front surface and a back surface opposed to the front surface, is arranged on the die pad with the front surface facing away from the die pad. The semiconductor die is electrically coupled to the electrically conductive leads. A package molding material is molded over the semiconductor die arranged on the die pad. A stress absorbing material contained within a cavity delimited by a peripheral wall on the front surface of the semiconductor die is positioned intermediate at least one selected portion of the front surface of the semiconductor die and the package molding material.

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