公开(公告)号：EP1804450A1

公开(公告)日：2007-07-04

申请号：EP05078051.9

申请日：2005-12-30

Applicant: STMicroelectronics Belgium N.V.

Inventor： Janssens, Erik

IPC: H04L27/26

CPC classification number: H04L5/0064 ,  H04L5/0007 ,  H04L5/0046 ,  H04L5/006

Abstract: A digital subscriber line system uses a multi-carrier transmission scheme in which a set of carriers are distributed across a frequency range. Transceiver units (12,61) are connected to each end of a line (31). The transceiver units (12,61), allocate data only to a sub-set of the total set of carriers (150) used by the transmission scheme and disable the unused carriers (160). The sub-set of carriers are positioned at the high frequency end of the frequency range. Reduced use of the lower frequency carriers reduces cross-talk in this band, improving Signal-to-noise ratio (SNR) and reach for other transceiver units.

Abstract translation: 数字用户线系统使用多载波传输方案，其中一组载波在频率范围内分布。 收发器单元（12,61）连接到线路（31）的每一端。 收发机单元（12,61）仅将数据分配给传输方案使用的总载波集合（150）的子集，并且禁用未使用的载波（160）。 载波子集位于频率范围的高频端。 较低频率载波的使用减少了该频带中的串扰，提高了信噪比（SNR），达到了其他收发器单元的目的。

公开(公告)号：EP1655667A2

公开(公告)日：2006-05-10

申请号：EP05447243.6

申请日：2005-11-04

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph ,  Charlier, Vincent ,  Rahaga, Tiana ,  Vandersmissen, Yves

IPC: G06F12/06

CPC classification number: G06F9/30149 ,  G06F9/322 ,  G06F9/328 ,  G06F12/0638

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialisation process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Abstract translation: 代码修补装置被提供用于具有存储指令代码的只读存储器和用于存储补丁码的另外的存储器的处理器。 多个补丁地址寄存器每个存储在只读存储器中要在其上执行补丁的地址。 比较器将处理器正在访问的只读存储器的地址与存储在寄存器中的地址进行比较。 控制单元根据比较选择来自只读存储器的代码或来自另外存储器的补丁码。 代码修补设备可以通过修正的代码来替代来自只读存储器的错误的代码行。 在初始化过程中，补丁代码被加载到另外的存储器中，寄存器加载了需要修补的地址。

公开(公告)号：EP1489521B1

公开(公告)日：2006-05-03

申请号：EP03447153.2

申请日：2003-06-16

Applicant: STMicroelectronics Belgium N.V.

Inventor： Levy, David

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1093 ,  G11C7/1006 ,  G11C7/1078

公开(公告)号：EP1503293A2

公开(公告)日：2005-02-02

申请号：EP03079181.8

申请日：2003-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT 2m, a second multiplier, an IFFT 2M, a 1 st half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(-jπn 2 α) for n=0:M-1, derived from the clock offset signal represented by α.

Abstract translation: 使用几个2M点传统傅立叶变换来描述M点分数傅里叶。 信号路径通过包括第一乘法器，零焊盘，FFT2m，第二乘法器，IFFT 2M，第一半元件和第三乘法器的一系列块馈送。 对于n = 0：M-1，第一乘法器和第三乘法器具有作为其他输入的值exp（-j pi n 2 alpha），从由alpha表示的时钟偏移信号导出。

公开(公告)号：EP1469590A1

公开(公告)日：2004-10-20

申请号：EP03076146.4

申请日：2003-04-17

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc

IPC: H03D7/14 ,  H03C1/54

CPC classification number: H03D7/1441 ,  H03C1/547 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D7/1491 ,  H03D2200/0043 ,  H03D2200/0084

Abstract: An up conversion mixer has a Gilbert cell arrangement including an input amplification part (BB) for producing an amplified signal coupled to a multiplication part (RF), the multiplication part being arranged to multiply the amplified signal by a local oscillator signal (LO) and output a mixed signal, the mixer also having a capacitor (90,100,15) coupled from a node between the input amplification part and the multiplication part, to a power supply line, for suppressing unwanted high frequency signal components of the output signal of the multiplication part. The linearity of such mixers can be improved considerably by this impedance on the source node of the switch transistors. This capacitance can be placed to either VSS or to VDD. Notably this improvement can be achieved with low power consumption since no additional power is needed for the increased performance.

Abstract translation: 上变频混频器具有吉尔伯特单元装置，该吉尔伯特单元装置包括用于产生耦合到乘法部分（RF）的放大信号的输入放大部分（BB），乘法部分被设置为将放大的信号乘以本地振荡器信号（LO）;以及 输出混合信号，该混频器还具有从输入放大部分和乘法部分之间的节点耦合到电源线的电容器（90,100,15），用于抑制乘法的输出信号的不需要的高频信号分量 部分。 这种混频器的线性度可以通过开关晶体管源极节点上的阻抗来显着提高。 该电容可以置于VSS或VDD。 值得注意的是，这种改进可以在低功耗下实现，因为不需要额外的功率来提高性能。

公开(公告)号：EP1434402A1

公开(公告)日：2004-06-30

申请号：EP02447272.2

申请日：2002-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio

IPC: H04L27/26 ,  H03H17/04

CPC classification number: H04L27/2662 ,  H04L27/2657

Abstract: A clock offset compensation arrangement has a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform based processing in the frequency domain. Compared to a polynomial type interpolation it can be easier to implement, and can achieve a closer approximation to a perfect interpolation. It can reduce the effects of non linear type errors introduced by truncation of higher powers. The arrangement can be applied to receivers or transmitters of multicarrier modems, or any application which needs rate adaption or synchronization.

Abstract translation: 时钟偏移补偿装置具有分数内插器，用于根据时钟偏移信号对采样输入信号应用三角内插。 它使用频域中的基于变换的处理。 与多项式插值相比，它可以更容易实现，并且可以更接近于完美的插值。 它可以减少由截断较高功率引入的非线性误差的影响。 该配置可以应用于多载波调制解调器的接收器或发射器，或者需要速率适配或同步的任何应用。

公开(公告)号：EP1422827A1

公开(公告)日：2004-05-26

申请号：EP02447228.4

申请日：2002-11-21

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/099 ,  H03L7/081 ,  H03L7/089

CPC classification number: H03L7/18 ,  H03L7/081 ,  H03L7/0893 ,  H03L7/0996

Abstract: A Phase-Locked Loop with multiphase clocks with

a main loop comprising a Phase Frequency Detector (1), a Main Charge Pump (2), a Main Loop Filter (3), a Multi-Phase Voltage Controlled Oscillator (4) and a Phase-switching Fractional Divider (5), coupled in series,
a calibration loop comprising a Calibration Charge Pump (6), a multiplexer (7) and Y Calibration Loop Filters (8), with Y being an integer,
a Control Logic (9) arranged to control said Phase-Switching Fractional Divider (5) and said multiplexer (7), and
a Reference Frequency Signal (10) applied to said Phase Frequency Detector (PFD)(1) and a calibration signal (11) applied to said calibration loop,
characterised in that the main loop comprises a Phase-adjusting block (12) coupled with a demultiplexer (13), wherein said Phase-adjusting block is arranged to receive correction signals from said calibration loop and said multiplexer is controlled by said Control Logic (9)

Abstract translation: 具有多相时钟的锁相环，主相包括相位检波器（1），主电荷泵（2），主回路滤波器（3），多相电压控制振荡器（4）和相位 控制逻辑（9），其包括校准电荷泵（6），多路复用器（7）和Y校准环路滤波器（8），Y为整数的校准回路（5） 布置成控制所述相位切换分数分割器（5）和所述多路复用器（7），以及施加到所述相位频率检测器（PFD）（1）的参考频率信号（10）和应用于所述校准 环路，其特征在于，主回路包括与解复用器（13）耦合的相位调整块（12），其中所述相位调整块被布置成从所述校准环路接收校正信号，并且所述多路复用器由所述控制逻辑 （9）

公开(公告)号：EP2180593A1

公开(公告)日：2010-04-28

申请号：EP08167383.2

申请日：2008-10-23

Applicant: STMicroelectronics Belgium N.V. ,  Semiconductor Ideas to The Market (ItoM) BV

Inventor： Terryn, Steven ,  Borremans, Marc ,  Goetschalckx, Paul

IPC: H03D7/16

CPC classification number: H03D7/161 ,  H03D7/166 ,  H03D2200/0047 ,  H03D2200/0082

Abstract: Methods and devices for the compensation for variations in the frequency drift of a free-running VCO/DCO (voltage/digital controlled oscillator), e.g. inside a frequency synthesizer, are described. In one aspect, the frequency drift of the high-frequency synthesizer is compensated by adjusting the frequency of the baseband signal.
A counter unit is used to determine the frequency offset between the frequency of the free-running oscillator and a reference clock. A difference signal is used to correct the upstream or downstream signal.

Abstract translation: 用于补偿自由运行的VCO / DCO（电压/数字控制振荡器）的频率漂移变化的方法和装置，例如， 在频率合成器内部进行描述。 一方面，通过调整基带信号的频率来补偿高频合成器的频率漂移。 计数器单元用于确定自由振荡器的频率与参考时钟之间的频率偏移。 差分信号用于校正上行或下行信号。

公开(公告)号：EP2045970A1

公开(公告)日：2009-04-08

申请号：EP07447055.0

申请日：2007-10-05

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph ,  Aerts, Wouter ,  Ryder, Martin

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04W72/1215 ,  H04W88/10

Abstract: Wireless transceiver apparatus is described for operating in a part of the RF spectrum in which a first wireless transceiver apparatus shares with a co-located second wireless transceiver apparatus.
The first wireless transceiver apparatus comprises:
a wireless transceiver unit;
an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus;

wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operational, or requests to be operational;
and wherein the arbitration interface is adapted to signal data about the first wireless transceiver apparatus during other time periods.

Abstract translation: 无线收发机装置描述了用于在RF频谱的一部分操作，其中，第一无线收发信机装置共享与协同定位的第二无线收发器装置。 第一无线收发器装置，包括：无线收发器单元; 仲裁接口，用于与在哪一个的访问进行仲裁第一无线收发信机装置和所述第二无线收发信机装置之间的RF频谱的共享部分仲裁实体接口; worin仲裁接口angepasst到信号timeperiods当无线收发器单元是可操作的，或请求可运行; 和worin仲裁接口angepasst以通知有关在其他时间段的第一无线收发器装置中的数据。

公开(公告)号：EP1753134B1

公开(公告)日：2008-05-28

申请号：EP05447184.2

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H03H17/06

CPC classification number: H03H17/0621 ,  H03H17/0685