公开(公告)号：US09378950B1

公开(公告)日：2016-06-28

申请号：US15051362

申请日：2016-02-23

Applicant: Stratio, Inc. ,  Stratio

Inventor： Jae Hyung Lee ,  Youngsik Kim ,  Yeul Na ,  Woo-Shik Jung

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02057 ,  H01L21/02082 ,  H01L21/02636 ,  H01L21/30604

Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.

Abstract translation: 一种用于去除在选择性外延生长工艺过程中形成的核的方法包括用一个或多个掩模层在衬底上外延生长第一组一个或多个半导体结构。 在一个或多个掩模层上形成第二组多个半导体结构。 该方法还包括在一个或多个半导体结构的第一组上形成一个或多个保护层。 多个半导体结构的第二组的至少一个子集从一个或多个保护层露出。 该方法还包括：在一个或多个半导体结构的第一组上形成一个或多个保护层之后，至少蚀刻多个半导体结构的第二组的子集。

公开(公告)号：JP6787786B2

公开(公告)日：2020-11-18

申请号：JP2016557040

申请日：2016-05-23

Applicant: ストレイティオ, インコーポレイテッド ,  STRATIO, INC.

Inventor： ジェヒュン リー ,  ヨル ナ ,  ヨンシク キム ,  ウーシク ジュン

IPC: H01L21/306 ,  H01L21/205

公开(公告)号：JP2018129536A

公开(公告)日：2018-08-16

申请号：JP2018078326

申请日：2018-04-16

Applicant: ストレイティオ, インコーポレイテッド ,  STRATIO, INC.

Inventor： ジェヒュン リー ,  ヨル ナ ,  ヨンシク キム ,  ウーシク ジュン

IPC: H01L31/10

CPC classification number: H01L31/1136 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14649 ,  H01L27/14689 ,  H01L31/1804 ,  H04N5/361 ,  H04N5/378

Abstract: 【課題】小さな暗電流、高い量子効率、強いチャンネル変調を有する光センサを提供する。 【解決手段】光を検知するためのデバイス100は、第1の型のドーパントを用いてドープされた第1の半導体領域104と、第2の型のドーパントを用いてドープされた第2の半導体領域106と、を含む。第2の半導体領域は、第1の半導体領域の上方に配置されている。デバイスは、ゲート絶縁層110と、ゲート112と、ソース114と、ドレイン116と、を含む。第2の半導体領域は、ゲート絶縁層のほうを向いて配置されている上面と、第2の半導体領域の上面に対して反対側に配置されている底面と、を有する。第2の半導体領域は、第2の半導体領域の上面を含む上側部分と、上側部分とは相互に排他的であり第2の半導体領域の底面を含む下側部分と、を有する。第1の半導体領域は、第2の半導体領域の上側部分及び下側部分の両方と接触している。 【選択図】図1A

公开(公告)号：EP3111466A1

公开(公告)日：2017-01-04

申请号：EP16750355.6

申请日：2016-05-23

Applicant: Stratio, Inc. ,  STRATIO

Inventor： LEE, Jae Hyung ,  NA, Yeul ,  KIM, Youngsik ,  JUNG, Woo-Shik

IPC: H01L21/02

CPC classification number: H01L21/3081 ,  H01L21/02057 ,  H01L21/02082 ,  H01L21/02636 ,  H01L21/30604

Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.

公开(公告)号：US20190221595A1

公开(公告)日：2019-07-18

申请号：US16167241

申请日：2018-10-22

Applicant: Stratio Inc.

Inventor： Jae Hyung LEE ,  Yeul NA ,  Youngsik KIM ,  Woo-Shik JUNG

IPC: H01L27/146 ,  H04N5/378 ,  H01L31/113 ,  H01L31/18

CPC classification number: H01L27/14616 ,  H01L27/14614 ,  H01L27/14649 ,  H01L27/14689 ,  H01L31/1136 ,  H01L31/1804 ,  H04N5/361 ,  H04N5/378

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

公开(公告)号：US10366884B1

公开(公告)日：2019-07-30

申请号：US16184984

申请日：2018-11-08

Applicant: Stratio

Inventor： Jaehyung Lee ,  Yeul Na ,  Youngsik Kim

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092

Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than, the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.

公开(公告)号：WO2022003217A1

公开(公告)日：2022-01-06

申请号：PCT/ES2020/070431

申请日：2020-07-03

Applicant: STRATIO BIG DATA INC SUCURSAL EN ESPAÑA

Inventor： OSCAR, Mendez ,  ROMAN, Martin ,  MARCO, Tulio ,  ROQUE, Vassal'lo

IPC: G06F16/90 ,  G06N5/02 ,  G06F21/00

Abstract: Se propone un método implementado por ordenador y un sistema electrónico para la gestión y el acceso a datos de una manera optimizada. La solución propuesta permite ofrecer una capa de datos, independiente del modelo físico de los datos, mediante una definición de negocio y semántica en base a ontologías. Una vez creada esta capa de datos, toda gestión y acceso al dato se realiza en base a dicha capa, lo que permite el acceso al dato en base a una definición de negocio, desacoplando todos los procesos/sistemas que explotan los datos de los modelos físicos de datos, y haciéndolos portables en diferentes escenarios.

公开(公告)号：US20230019977A1

公开(公告)日：2023-01-19

申请号：US17684124

申请日：2022-03-01

Applicant: Stratio, Inc.

Inventor： Jae Hyung LEE ,  Yeul NA ,  Youngsik KIM ,  Woo-Shik JUNG

IPC: H01L27/146 ,  H01L31/113 ,  H01L31/18 ,  H04N5/378

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

公开(公告)号：US11264418B2

公开(公告)日：2022-03-01

申请号：US16167241

申请日：2018-10-22

Applicant: Stratio Inc.

Inventor： Jae Hyung Lee ,  Yeul Na ,  Youngsik Kim ,  Woo-Shik Jung

IPC: H01L27/146 ,  H01L31/113 ,  H01L31/18 ,  H04N5/378 ,  H04N5/361

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

公开(公告)号：US20210343528A1

公开(公告)日：2021-11-04

申请号：US17289205

申请日：2018-11-09

Applicant: STRATIO

Inventor： Jae Hyung LEE ,  Yaul NA ,  Youngsik KIM

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092

Abstract: A method for obtaining a semiconductor island includes epitaxially growing a semiconductor structure over a substrate with a mask layer defining a region not covered by the mask layer. The semiconductor structure includes a first portion located adjacent to the mask layer and a second portion located away from the mask layer. The first portion has a first height that is less than a second height of a portion of the mask layer located adjacent to the first portion. The second portion has a third height that is equal to, or greater than the second height. The method also includes forming a filling layer over at least the first portion; and, subsequently removing at least a portion of the semiconductor structure that is located above the second height. Devices made by this method are also disclosed.