公开(公告)号：TW201417185A

公开(公告)日：2014-05-01

申请号：TW102131402

申请日：2013-08-30

Applicant: 增普拓尼克斯公司 ,  ZIPTRONIX, INC.

Inventor： 恩奎斯特 保羅M ,  ENQUIST, PAUL M. ,  方坦 蓋厄斯 吉歐曼 二世 ,  FOUNTAIN, GAIUS GILLMAN JR.

IPC: H01L21/324 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 本發明係關於一種整合具有具一第一絕緣材料及一第一接觸結構之一第一表面之一第一基板與具有具一第二絕緣材料及一第二接觸結構之一第二表面之一第二基板之方法。該第一絕緣材料直接接合至該第二絕緣材料。移除該第一基板之一部分以留下一剩餘部分。將具有與該第一基板之一熱膨脹係數(CTE)實質上相同之一CTE之一第三基板接合至該剩餘部分。加熱經接合基板以促進該第一接觸結構與該第二接觸結構之間之電接觸。在加熱之後移除該第三基板以提供具有可靠電接觸之一經接合結構。

Abstract in simplified Chinese: 本发明系关于一种集成具有具一第一绝缘材料及一第一接触结构之一第一表面之一第一基板与具有具一第二绝缘材料及一第二接触结构之一第二表面之一第二基板之方法。该第一绝缘材料直接接合至该第二绝缘材料。移除该第一基板之一部分以留下一剩余部分。将具有与该第一基板之一热膨胀系数(CTE)实质上相同之一CTE之一第三基板接合至该剩余部分。加热经接合基板以促进该第一接触结构与该第二接触结构之间之电接触。在加热之后移除该第三基板以提供具有可靠电接触之一经接合结构。

公开(公告)号：TW201733009A

公开(公告)日：2017-09-16

申请号：TW105141779

申请日：2016-12-16

Applicant: 增普拓尼克斯公司 ,  ZIPTRONIX, INC.

Inventor： 恩奎斯特 保羅M ,  ENQUIST, PAUL M. ,  方騰 蓋烏斯 吉爾曼 ,  FOUNTAIN, GAIUS GILLMAN ,  狄拉克魯茲 賈維爾A ,  DELACRUZ, JAVIER A.

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L23/5226 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/80 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593

Abstract: 一種接合裝置結構包括：第一基板，其具有第一組傳導性接觸結構(較佳的是連接到一裝置或電路)，並且具有在第一基板上相鄰接觸結構的第一非金屬性區域；第二基板，其具有第二組傳導性接觸結構(較佳的是連接到一裝置或電路)，並且具有在第二基板上相鄰接觸結構的第二非金屬性區域；以及在第一組和第二組接觸結構之間的接觸接合介面，其是藉由將第一非金屬性區域接觸接合至第二非金屬性區域所形成。接觸結構包括在兩個基板上是非平行的長形接觸特徵(諸如個別線路或在格柵中連接的線路)，而在相交點接觸。因而，改善了對準容限同時使凹陷和寄生電容最小化。

Abstract in simplified Chinese: 一种接合设备结构包括：第一基板，其具有第一组传导性接触结构(较佳的是连接到一设备或电路)，并且具有在第一基板上相邻接触结构的第一非金属性区域；第二基板，其具有第二组传导性接触结构(较佳的是连接到一设备或电路)，并且具有在第二基板上相邻接触结构的第二非金属性区域；以及在第一组和第二组接触结构之间的接触接合界面，其是借由将第一非金属性区域接触接合至第二非金属性区域所形成。接触结构包括在两个基板上是非平行的长形接触特征(诸如个别线路或在格栅中连接的线路)，而在相交点接触。因而，改善了对准容限同时使凹陷和寄生电容最小化。

公开(公告)号：SG2011091576A

公开(公告)日：2015-02-27

申请号：SG2011091576

申请日：2004-02-06

Applicant: ZIPTRONIX INC

Inventor： TONG QIN-YI ,  ENQUIST PAUL M ,  ROSE ANTHONY SCOT

IPC: H01L21/60 ,  H01L21/98

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：IL198903A

公开(公告)日：2011-09-27

申请号：IL19890309

申请日：2009-05-24

Applicant: ZIPTRONIX INC

IPC: H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.

公开(公告)号：CA2543100A1

公开(公告)日：2005-05-12

申请号：CA2543100

申请日：2004-10-20

Applicant: ZIPTRONIX INC

Inventor： ENQUIST PAUL M

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/467 ,  H01L21/98 ,  H01L23/48 ,  H01L23/535 ,  H01L23/538 ,  H01L25/065

Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.

公开(公告)号：CA2515375C

公开(公告)日：2013-09-24

申请号：CA2515375

申请日：2004-02-06

Applicant: ZIPTRONIX INC

Inventor： TONG QIN-YI ,  ENQUIST PAUL M ,  ROSE ANTHONY SCOT

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/98

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：CA2404270C

公开(公告)日：2011-02-22

申请号：CA2404270

申请日：2001-03-22

Applicant: ZIPTRONIX INC

Inventor： ENQUIST PAUL M

IPC: H01L21/768 ,  H01L31/04 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/98 ,  H01L27/00

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device (14) having a substrate (20) to an element (10) and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semi-conductor device. Interconnections (51) may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices (165) to an element (163), and the element may have recesses (167) in which the semiconductor devices are disposed. A conductor array (78) having a plurality of contact structures may be formed on an exposed surface of the semiconductor device (77), vias may be formed through the semiconductor device to device regions, and interconnection (81, 82, 83) may be formed between said device regions and said contact structures.

公开(公告)号：IL189173D0

公开(公告)日：2008-06-05

申请号：IL18917308

申请日：2008-02-03

Applicant: ZIPTRONIX INC

IPC: H01L20100101

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：IL175044D0

公开(公告)日：2006-08-20

申请号：IL17504406

申请日：2006-04-20

Applicant: ZIPTRONIX INC

IPC: H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

Abstract: A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.

公开(公告)号：AU2005227167A1

公开(公告)日：2005-10-06

申请号：AU2005227167

申请日：2005-02-23

Applicant: ZIPTRONIX INC

Inventor： FOUNTAIN GAIUS G JR ,  ENQUIST PAUL M ,  PETTEWAY CARL T

IPC: H01L23/495

Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.