公开(公告)号：KR102198601B1

公开(公告)日：2021-01-05

申请号：KR1020190043097

申请日：2019-04-12

Applicant: 김창선 ,  국민대학교산학협력단

Inventor： 민경식 ,  김창선

IPC: H02N11/00 ,  H01L35/00 ,  H02M1/08 ,  H02M3/156

Abstract: 열전발전기제어방법및 장치를개시한다. 본실시예에의하면, 최대전력점추적(MPPT: Maximum Power Point Tracking) 및영전류스위칭(ZCS: Zero-Current Switching)을기반으로에너지하베스팅장치에서복수의열전발전기를이용하는경우에도생산전력량대비전달전력량의효율성이떨어지지않는열전발전기제어장치를제공한다.

公开(公告)号：KR102109844B1

公开(公告)日：2020-05-12

申请号：KR1020180035360

申请日：2018-03-27

Applicant: 국민대학교산학협력단

Inventor： 이현정 ,  백종찬 ,  박현우 ,  민경식 ,  오정헌 ,  최현주 ,  김윤희

IPC: H01L35/32 ,  H01L35/04 ,  H01L35/12 ,  H01L35/34

公开(公告)号：KR1020170108627A

公开(公告)日：2017-09-27

申请号：KR1020160032826

申请日：2016-03-18

Applicant: 국민대학교산학협력단

Inventor： 민경식 ,  트롱녹손

IPC: G11C13/00 ,  H03K19/177 ,  G11C11/54 ,  G06N3/063

Abstract: 본발명은이미지인식이진멤리스터의두 개의동일한크로스바어레이로구성되는트윈크로스바회로를갖는신경모방멤리스터크로스바회로를제공하기위한것으로서, N X M 멤리스터로구성되는멤리스터어레이로이루어지고, 이미지벡터를저장하는제 1 크로스바어레이와, 상기제 1 크로스바어레이와트윈크로스바구조를갖는멤리스터어레이로이루어지며, 상기제 1 크로스바어레이의입력벡터의반전된벡터를입력받아, 반전된이미지벡터를저장하는제 2 크로스바어레이와, 상기제 1 크로스바어레이의출력벡터및 상기제 2 크로스바어레이의출력벡터를각각감산하여유사성의양을측정하는감산기와, 상기감산기에서측정된유사성양을저장된화상벡터와비교하여유사도가가장일치하는저장된이미지벡터를선택하여출력하는승자독점회로부(winner-take-all circuit)로구성되는데있다.

Abstract translation: 本发明提供了一种神经模仿忆阻器纵横式电路，其具有由两个相同的图像感知式二元忆阻器的相交叉阵列组成的双横杆电路，其包括由NXM忆阻器组成的忆阻器阵列， 它由具有第一横杆阵列和所述第一交叉杆阵列和用于存储，接收所述交叉杆阵列矢量的第一输入端的反向矢量的双横杆结构的膜晶闸管阵列，存储权利要求的反转图像向量 减法器，用于减去第一交叉开关阵列的输出向量和第二交叉开关阵列的输出向量以测量相似量; 还有一个赢家通吃电路，用于选择和输出最接近匹配的存储图像矢量 还有用。

公开(公告)号：KR101282884B1

公开(公告)日：2013-07-17

申请号：KR1020120028470

申请日：2012-03-20

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식 ,  정철문

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C7/109 ,  G11C7/1096 ,  G11C7/22 ,  G11C13/0002

Abstract: PURPOSE: Complementary memristor driving circuit and control method of the complementary memristor are provided to increase a size of array by minimizing sneak-path leakage current in case of reading operation. CONSTITUTION: Input data are received. First writing operation to a specific cell with respect to the received input data is performed (S32). Second writing operation to a specific cell with respect to the received input data after the first writing operation is performed (S42). The second writing operation is completed based on resistance variation of the specific cell (S70). The voltage applied in the second writing operation is greater than the voltage applied in the first writing operation. [Reference numerals] (AA) Start; (BB,DD,EE) No; (CC,FF,GG) Yes; (HH) End; (S20) Is an input '1' ?; (S32) First session first stage writing starts; (S34) Second session first stage writing starts; (S42,S44) Second stage writing starts; (S52,S54) The second stage writing works; (S62,S64) Is a reference voltage less than the voltage of a sensor node ?; (S70) The second stage writing ends

Abstract translation: 目的：提供互补忆阻器驱动电路和互补忆阻器的控制方法，以便在读取操作的情况下最大限度地减少潜行漏电流来增加阵列的尺寸。 构成：接收输入数据。 执行相对于接收的输入数据对特定单元的写入操作（S32）。 在执行第一次写入操作之后相对于所接收的输入数据对特定单元进行第二次写入操作（S42）。 基于特定单元的电阻变化完成第二写入操作（S70）。 在第二写入操作中施加的电压大于在第一写入操作中施加的电压。 （附图标记）（AA）开始; （BB，DD，EE）否; （CC，FF，GG）是; （HH）结束; （S20）是输入“1”吗？ （S32）第一课开始写作; （S34）第二课开始写作; （S42，S44）第二阶段写作开始; （S52，S54）第二阶段写作工作; （S62，S64）是比传感器节点的电压小的参考电压吗？ （S70）第二阶段写入结束

公开(公告)号：KR1020120068347A

公开(公告)日：2012-06-27

申请号：KR1020100129935

申请日：2010-12-17

Applicant: 국민대학교산학협력단

Inventor： 민경식 ,  조관희

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C7/1048 ,  G11C7/109 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2227 ,  H03K19/0175

Abstract: PURPOSE: A low power memristor driving circuit and a driving method thereof are provided to prevent a power loss by properly controlling an amount of currents. CONSTITUTION: A first low power driving control unit(200) generates a first internal write control signal of a memristor. A first operation signal applying unit applies a driving operation voltage to the first low power driving control unit. A first precharge unit(300) supplies a driving voltage of the memristor to the first low power driving control unit. A first write current applying unit(350) supplies a write current to the low power memristor driving circuit. An operating voltage applying unit(800) supplies an operation voltage to the low power memristor driving circuit.

Abstract translation: 目的：提供低功率忆阻器驱动电路及其驱动方法，以通过适当地控制电流量来防止功率损耗。 构成：第一低功率驱动控制单元（200）产生忆阻器的第一内部写入控制信号。 第一操作信号施加单元向第一低功率驱动控制单元施加驱动操作电压。 第一预充电单元（300）将忆阻器的驱动电压提供给第一低功率驱动控制单元。 第一写入电流施加单元（350）向低功率忆阻器驱动电路提供写入电流。 工作电压施加单元（800）向低功率忆阻器驱动电路提供工作电压。

公开(公告)号：KR1020110021296A

公开(公告)日：2011-03-04

申请号：KR1020090079006

申请日：2009-08-26

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G11C11/413 ,  G11C11/4193 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C7/1096 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/2227

Abstract: PURPOSE: A SRAM circuit is provided to reduce total leakage current by reducing the leakage current below threshold voltage and an oxide-tunneling leakage current. CONSTITUTION: A prechage part is comprised of first, second, third PMOs transistor(MP1,MP2, MP3). The prechage part is driven by the voltage of power voltage terminal. At least one SRAM cell includes a first NMOS transistor(MN1), a fourth PMOS transistor(MP4), a second NMOS transistor(MN2), and a fifth PMOS transistor(MP5). The SARM cell stores memory information. A source line driver is comprised of the fifth NMOS transistor. The source line driver dynamically arbitrarily controls the source line voltage of a memory cell from a driving voltage to a ground voltage. At least one word line driver reduces the oxide tunneling leakage current of the SRAM One or more write driver reduce voltage swing of a bit line and a bit line bar. The write driver reduces the oxide tunneling leakage current of the SRAM cell.

Abstract translation: 目的：提供SRAM电路，通过将漏电流降低到阈值电压和氧化物隧穿漏电流来减少总泄漏电流。 构成：前置部分由第一，第二，第三PMO晶体管（MP1，MP2，MP3）组成。 前置部分由电源电压端子驱动。 至少一个SRAM单元包括第一NMOS晶体管（MN1），第四PMOS晶体管（MP4），第二NMOS晶体管（MN2）和第五PMOS晶体管（MP5）。 SARM单元存储存储器信息。 源极线驱动器由第五个NMOS晶体管组成。 源极线驱动器动态地任意地控制从驱动电压到接地电压的存储器单元的源极线电压。 至少一个字线驱动器减少SRAM的氧化物隧道漏电流一个或多个写驱动器减少位线和位线条的电压摆幅。 写驱动器减少了SRAM单元的氧化物隧道漏电流。

公开(公告)号：KR101015543B1

公开(公告)日：2011-02-16

申请号：KR1020090058054

申请日：2009-06-29

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G05F3/26 ,  G05F1/56

Abstract: 본 발명은 기준전압발생기 회로에 관한 것으로, 보다 상세하게는 도 2와 같은 회로배치를 갖는 기준전압발생기 회로에 관한 것으로, 본 발명의 기준전압발생기 회로는 종래의 기준전압발생기 대비 레이아웃 면적을 50% 정도 절약할 수 있고, 또한 종래 기준전압발생기 회로 대비 대략 30% 정도의 전력 소비를 줄일 수 있다.
기준전압발생기, 면적, 전력소모

公开(公告)号：KR1020080101353A

公开(公告)日：2008-11-21

申请号：KR1020070047993

申请日：2007-05-17

Applicant: 국민대학교산학협력단

Inventor： 민경식

IPC: G11C29/00

CPC classification number: G11C29/70 ,  G11C7/10 ,  G11C8/10

Abstract: A data line redundancy circuit is provided to be used in a redundancy circuit having small data pitch by making a circuit simpler than the conventional device. A data line redundancy circuit includes N+1 data lines are composed of n data line and redundant data line, n output lines, 2n data switches connecting each data lien to output line alternately, n shift logic circuits controlling a pair of data line switches, 2n data line switches connecting(n')-th data line,(n)-th data line,(n")-th data line alternately.

Abstract translation: 通过使电路比传统的器件简单，提供了用于具有小数据间距的冗余电路中的数据线冗余电路。 数据线冗余电路包括N + 1条数据线，由n条数据线和冗余数据线，n条输出线，2n条数据开关组成，每条数据交替连接到输出线，n条逻辑电路控制一对数据线开关， 2n数据线交替地连接（n'）数据线，（n）数据线，（n“）数据线。