公开(公告)号：KR1020110000784A

公开(公告)日：2011-01-06

申请号：KR1020090058054

申请日：2009-06-29

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G05F3/26 ,  G05F1/56

Abstract: PURPOSE: A reference voltage generator circuit is provided to implement small area and low power consumption while having same performance as a conventional circuit. CONSTITUTION: A reference voltage generating circuit comprises a current mirror, a second resistor(R2), and a first NMOSFET(MN1). First and second bipolar transistors(Q1,Q2) and a first resistor(R1) generates a reference current. The current mirror is comprised of first, second, and third current paths. The first current path of the current mirror is connected to the emitter of the first bipolar transistor. The second current path of the current mirror is connected to one terminal of the first resistor. The third current path of the current mirror is connected to one terminal of the second resistor.

Abstract translation: 目的：提供参考电压发生器电路，以实现小面积和低功耗，同时具有与常规电路相同的性能。 构成：参考电压产生电路包括电流镜，第二电阻（R2）和第一NMOSFET（MN1）。 第一和第二双极晶体管（Q1，Q2）和第一电阻器（R1）产生参考电流。 电流镜由第一，第二和第三电流路径组成。 电流镜的第一电流通路连接到第一双极晶体管的发射极。 电流镜的第二电流通路连接到第一电阻的一个端子。 电流镜的第三电流通路连接到第二电阻的一个端子。

公开(公告)号：KR101046403B1

公开(公告)日：2011-07-05

申请号：KR1020090079006

申请日：2009-08-26

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G11C11/413 ,  G11C11/4193 ,  G11C11/419

Abstract: 본 발명은 에스램 (SRAM) 회로에 관한 것으로, 보다 상세하게는 도 2와 같은 회로 구성을 포함하는 에스램 (SRAM) 회로에 관한 것으로, 본 발명의 에스램 (SRAM) 회로는 종래의 에스램 (SRAM) 회로와 비교하여 누설전류 소비를 75 ℃에서 약 10%, 25 ℃에서 약 20%, -25 ℃에서 약 40%를 줄일 수 있다.
에스램, 저전력, 누설전류억제, 옥사이드 터널링

Abstract translation: 本发明涉及一种SRAM电路，更具体地涉及一种包括如图2所示的电路配置的SRAM电路，其中本发明的SRAM电路包括常规的SRAM 与传统的SRAM电路相比，在75°C时泄漏电流消耗可降低约10％，在25°C时降低约20％，在-25°C时降低约40％。

公开(公告)号：KR101282884B1

公开(公告)日：2013-07-17

申请号：KR1020120028470

申请日：2012-03-20

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식 ,  정철문

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C7/109 ,  G11C7/1096 ,  G11C7/22 ,  G11C13/0002

Abstract: PURPOSE: Complementary memristor driving circuit and control method of the complementary memristor are provided to increase a size of array by minimizing sneak-path leakage current in case of reading operation. CONSTITUTION: Input data are received. First writing operation to a specific cell with respect to the received input data is performed (S32). Second writing operation to a specific cell with respect to the received input data after the first writing operation is performed (S42). The second writing operation is completed based on resistance variation of the specific cell (S70). The voltage applied in the second writing operation is greater than the voltage applied in the first writing operation. [Reference numerals] (AA) Start; (BB,DD,EE) No; (CC,FF,GG) Yes; (HH) End; (S20) Is an input '1' ?; (S32) First session first stage writing starts; (S34) Second session first stage writing starts; (S42,S44) Second stage writing starts; (S52,S54) The second stage writing works; (S62,S64) Is a reference voltage less than the voltage of a sensor node ?; (S70) The second stage writing ends

Abstract translation: 目的：提供互补忆阻器驱动电路和互补忆阻器的控制方法，以便在读取操作的情况下最大限度地减少潜行漏电流来增加阵列的尺寸。 构成：接收输入数据。 执行相对于接收的输入数据对特定单元的写入操作（S32）。 在执行第一次写入操作之后相对于所接收的输入数据对特定单元进行第二次写入操作（S42）。 基于特定单元的电阻变化完成第二写入操作（S70）。 在第二写入操作中施加的电压大于在第一写入操作中施加的电压。 （附图标记）（AA）开始; （BB，DD，EE）否; （CC，FF，GG）是; （HH）结束; （S20）是输入“1”吗？ （S32）第一课开始写作; （S34）第二课开始写作; （S42，S44）第二阶段写作开始; （S52，S54）第二阶段写作工作; （S62，S64）是比传感器节点的电压小的参考电压吗？ （S70）第二阶段写入结束

公开(公告)号：KR1020110021296A

公开(公告)日：2011-03-04

申请号：KR1020090079006

申请日：2009-08-26

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G11C11/413 ,  G11C11/4193 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C7/1096 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/2227

Abstract: PURPOSE: A SRAM circuit is provided to reduce total leakage current by reducing the leakage current below threshold voltage and an oxide-tunneling leakage current. CONSTITUTION: A prechage part is comprised of first, second, third PMOs transistor(MP1,MP2, MP3). The prechage part is driven by the voltage of power voltage terminal. At least one SRAM cell includes a first NMOS transistor(MN1), a fourth PMOS transistor(MP4), a second NMOS transistor(MN2), and a fifth PMOS transistor(MP5). The SARM cell stores memory information. A source line driver is comprised of the fifth NMOS transistor. The source line driver dynamically arbitrarily controls the source line voltage of a memory cell from a driving voltage to a ground voltage. At least one word line driver reduces the oxide tunneling leakage current of the SRAM One or more write driver reduce voltage swing of a bit line and a bit line bar. The write driver reduces the oxide tunneling leakage current of the SRAM cell.

Abstract translation: 目的：提供SRAM电路，通过将漏电流降低到阈值电压和氧化物隧穿漏电流来减少总泄漏电流。 构成：前置部分由第一，第二，第三PMO晶体管（MP1，MP2，MP3）组成。 前置部分由电源电压端子驱动。 至少一个SRAM单元包括第一NMOS晶体管（MN1），第四PMOS晶体管（MP4），第二NMOS晶体管（MN2）和第五PMOS晶体管（MP5）。 SARM单元存储存储器信息。 源极线驱动器由第五个NMOS晶体管组成。 源极线驱动器动态地任意地控制从驱动电压到接地电压的存储器单元的源极线电压。 至少一个字线驱动器减少SRAM的氧化物隧道漏电流一个或多个写驱动器减少位线和位线条的电压摆幅。 写驱动器减少了SRAM单元的氧化物隧道漏电流。

公开(公告)号：KR101015543B1

公开(公告)日：2011-02-16

申请号：KR1020090058054

申请日：2009-06-29

Applicant: 국민대학교산학협력단 ,  광운대학교 산학협력단

Inventor： 민경식

IPC: G05F3/26 ,  G05F1/56

Abstract: 본 발명은 기준전압발생기 회로에 관한 것으로, 보다 상세하게는 도 2와 같은 회로배치를 갖는 기준전압발생기 회로에 관한 것으로, 본 발명의 기준전압발생기 회로는 종래의 기준전압발생기 대비 레이아웃 면적을 50% 정도 절약할 수 있고, 또한 종래 기준전압발생기 회로 대비 대략 30% 정도의 전력 소비를 줄일 수 있다.
기준전압발생기, 면적, 전력소모

公开(公告)号：KR102251043B1

公开(公告)日：2021-05-12

申请号：KR1020200005840

申请日：2020-01-16

Applicant: 국민대학교산학협력단

Inventor： 민경식

IPC: G11C13/00

Abstract: 본발명의실시예에따른메모리장치는입력데이터에포함된제1속성입력정보에상응하는입력신호와, 저장된제1저장데이터에따라, 제1멤리스터신호를출력하는제1멤리스터어레이회로, 상기입력데이터에포함된제2속성입력정보에상응하는입력신호와, 저장된제2저장데이터에따라, 제2멤리스터신호를출력하는제2멤리스터어레이회로및 상기제1멤리스터신호와상기제2멤리스터신호에기초하여, 상기제1멤리스터신호및 상기제2멤리스터신호에상응하는제3멤리스터신호를출력하는제3멤리스터어레이회로를포함한다.

公开(公告)号：KR102154834B1

公开(公告)日：2020-09-10

申请号：KR1020180036574

申请日：2018-03-29

Applicant: 국민대학교산학협력단

Inventor： 민경식

IPC: G06N3/063 ,  G11C11/4091

公开(公告)号：KR101174800B1

公开(公告)日：2012-08-20

申请号：KR1020100129935

申请日：2010-12-17

Applicant: 국민대학교산학협력단

Inventor： 민경식 ,  조관희

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

Abstract: 본발명은저전력멤리스터구동회로에관한것이다. 특히본 발명은데이터를쓰는동작에서저전력구동회로를통하여멤리스터에전류가흐르는구간을최소화시켜구동에필요한전류만흐르게하는저전력멤리스터구동회로에관한것이다.본발명은 '1'(high) 입력데이터에대응하는내부데이터신호를생성하는저전력멤리스터구동회로에있어서, 상기멤리스터의제1내부쓰기제어신호를생성하는제1저전력구동제어부, 상기제1저전력구동제어부에구동동작전압을인가하는제1동작신호인가부, 상기제1저전력구동제어부에상기멤리스터의구동전압을공급하는제1프리차지부, 저전력멤리스터구동회로에쓰기전류를공급하는제1쓰기전류인가부, 상기저전력멤리스터구동회로에동작전압을공급하는구동전압인가부, 상기제1내부쓰기제어신호에의하여상기내부데이터신호가생성되는것을특징으로한다.

公开(公告)号：KR1020170108619A

公开(公告)日：2017-09-27

申请号：KR1020160032810

申请日：2016-03-18

Applicant: 국민대학교산학협력단

Inventor： 민경식 ,  신상학

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/10

Abstract: 본발명은이전의고정기준방식보다판독전압마진을개선하기위해순수한멤리스터어레이(pure memristor array) 내에서선택된셀의위치와선택되지않은셀의데이터패턴에따라기준전압이변경될수 있는동적기준방식을갖는저항메모리읽기회로및 구동방법을제공하기위한것으로서, 전처리판독(PRE_RD) 펄스에의해구동되어각 열별로감지된기준전압을감지하는전처리판독기(PRE_RD)와, N X M 멤리스터로구성되는순수한멤리스터어레이로이루어지고, 메인판독기(MAIN_RD) 펄스에의해구동되어상기전처리판독기(PRE_RD)에서감지된기준전압을이용하여선택된셀을판독하는메인판독기(MAIN_RD)와, 상기메인판독기(MAIN_RD)에서선택된셀과선택되지않은셀에서각각감지된출력전압을열-라인별기준전압과비교하여열(column) 별로기준전압이가장낮은저항상태( 'L') 및가장높은저항상태( 'H')의중간전압으로변경하는열(column) 감지증폭기를포함하여구성되는데있다.

Abstract translation: 动态地基于系统的本发明，可以改变根据细胞非选定位置和纯忆阻器阵列（纯忆阻器阵列）中所选择的单元的数据图案中的电压基准，以改善比以前的固定参考方法所读取的电压裕 （PRE_RD），其由预读出（PRE_RD）脉冲驱动并感测每列所感测的参考电压，以及由NXM忆阻器组成的纯存储元件 它包括一个晶闸管阵列，主读出器（MAIN_RD）由脉冲和通过使用由所述预处理读取器（PRE-RD）检测到的参考电压，从主读取器选择读取所选择的小区的主读出器（MAIN_RD）驱动（MAIN_RD） 通过将由单元和未选单元感测的输出电压与每列参考电压进行比较来确定最高电阻状态（'L'）和最高电阻状态（'H'）， 有由包括热（列）读出放大器，以改变中间电压。

公开(公告)号：KR100833791B1

公开(公告)日：2008-05-29

申请号：KR1020070035805

申请日：2007-04-12

Applicant: 국민대학교산학협력단

Inventor： 민경식

IPC: G11C5/14

CPC classification number: G11C5/147 ,  H03K3/356113 ,  H03K19/018521

Abstract: A level shifter circuit is provided to perform level shift operation well even though voltage level difference between a low voltage power supply port and a high voltage power supply port is high. A level shifter circuit changes a voltage waveform with a voltage level of a low voltage power supply port(VDDL) into a voltage waveform with a voltage level of a high voltage power supply port(VDDH). The level shifter circuit includes a main level shifter circuit, a sub level shifter circuit, a first load capacitor, a second load capacitor and a first inverter(IV1). The main level shifter circuit comprises a first PMOS transistor(MP1), a second PMOS transistor(MP2), a first NMOS transistor(MN1) and a second NMOS transistor(MN2). The sub level shifter circuit comprises a third PMOS transistor(MP3), a fourth PMOS transistor(MP4), a fifth PMOS transistor(MP5), a sixth PMOS transistor(MP6), a third NMOS transistor(MN3) and a fourth NMOS transistor(MN4). The first inverter is formed between the low voltage power supply port and a ground port(VSS).

Abstract translation: 即使在低电压电源端口和高压电源端口之间的电压电平差高的情况下，也提供了电平移位电路来进行电平移位操作。 电平移位器电路将具有低电压电源端口（VDDL）的电压电平的电压波形改变成具有高电压电源端口（VDDH）的电压电平的电压波形。 电平移位电路包括主电平移位电路，副电平移位电路，第一负载电容器，第二负载电容器和第一逆变器（IV1）。 主电平移位器电路包括第一PMOS晶体管（MP1），第二PMOS晶体管（MP2），第一NMOS晶体管（MN1）和第二NMOS晶体管（MN2）。 子电平移位器电路包括第三PMOS晶体管（MP3），第四PMOS晶体管（MP4），第五PMOS晶体管（MP5），第六PMOS晶体管（MP6），第三NMOS晶体管（MN3）和第四NMOS晶体管 （MN4）。 第一个逆变器形成在低压电源端口和接地端口（VSS）之间。