公开(公告)号：KR102010303B1

公开(公告)日：2019-08-13

申请号：KR1020180005241

申请日：2018-01-15

Applicant: 국방과학연구소

Inventor： 정진우 ,  류지호 ,  주태환 ,  김기철 ,  박일현 ,  서종우

IPC: H01Q3/36

公开(公告)号：KR101995490B1

公开(公告)日：2019-07-02

申请号：KR1020180090035

申请日：2018-08-01

Applicant: 국방과학연구소

Inventor： 주태환 ,  서종우 ,  류지호 ,  김기철 ,  황찬호 ,  김민성 ,  이철훈

IPC: G01R29/08

公开(公告)号：KR100450258B1

公开(公告)日：2004-12-30

申请号：KR1019980058873

申请日：1998-12-26

Applicant: 국방과학연구소

Inventor： 김기철 ,  정명득 ,  정해원 ,  우병일 ,  김종명

IPC: H01L29/868

Abstract: PURPOSE: A structure of a pin diode and a method of manufacturing the same are to minimize the forward resistance by enhancing a surface area of an Ohmic metal layer to be formed on an upper portion of a n-typed layer of high density. CONSTITUTION: A pin diode comprises a semiconductor substrate(11) having a protrusion, a n-typed layer(12) formed on the protrusion of the substrate, a buffer layer(13), a p-typed layer(14), a n-typed layer(14) formed on a slanted surface of the protrusion and the substrate, Ohmic metal layers each formed the p-typed layer and the n-typed layer, air-bridge metal layers each contacted with a region of the Ohmic metal layer. The semiconductor substrate is made of a compound of Ga and As. The n-typed layer and p-typed layer are formed by an epitaxial growing layer.

Abstract translation: 目的：PIN二极管的结构及其制造方法的结构是通过增加要在高密度n型层的上部形成的欧姆金属层的表面积来使正向电阻最小化。 本发明公开了一种PIN二极管，包括：具有突起的半导体衬底（11），形成在衬底的突起上的n型层（12），缓冲层（13），p型层（14），n 形成在突起和衬底的倾斜表面上的欧姆金属层，各自形成p型层和n型层的欧姆金属层，空气桥金属层各自与欧姆金属层的区域接触 。 半导体衬底由Ga和As的化合物制成。 n型层和p型层由外延生长层形成。

公开(公告)号：KR100450259B1

公开(公告)日：2004-09-30

申请号：KR1019990003764

申请日：1999-02-04

Applicant: 국방과학연구소

Inventor： 김기철 ,  정명득 ,  정해원 ,  우병일 ,  김종명

IPC: H01L29/868

Abstract: PURPOSE: A pin diode is to reduce a forward resistance by forming a n-typed Ohmic metal layer on an exposed side of a n-typed epitaxial layer and a substrate near the epitaxial layer. CONSTITUTION: A pin diode comprises a substrate(31) with a step being formed between a portion to be formed with the pin diode and the remainder portion, a n-typed epitaxial layer(32) formed on the substrate to be formed with the pin diode and having a trapezoidal cross section, a buffer layer(33), a p-typed epitaxial layer(34), a p-typed Ohmic metal layer(35) formed on the p-typed epitaxial layer, a n-typed Ohmic metal layer(38) formed on an exposed side of the n-typed epitaxial layer and the substrate near the epitaxial layer.

Abstract translation: 目的：PIN二极管是通过在n型外延层和靠近外延层的衬底的暴露侧上形成n型欧姆金属层来降低正向电阻。 本发明公开了一种PIN二极管，包括：衬底（31），在待形成PIN二极管的部分和剩余部分之间形成台阶;形成在衬底上的n型外延层（32） 二极管并具有梯形截面，缓冲层（33），p型外延层（34），在p型外延层上形成的p型欧姆金属层（35），n型欧姆金属 形成在n型外延层的暴露侧上的层（38）和靠近外延层的衬底。

公开(公告)号：KR100429388B1

公开(公告)日：2004-04-29

申请号：KR1020020023784

申请日：2002-04-30

Applicant: 국방과학연구소

Inventor： 정명득 ,  우병일 ,  정해원 ,  김종명 ,  김기철

IPC: H01L29/868

Abstract: PURPOSE: A PIN diode and a method for manufacturing the same are provided to be capable of reducing the leakage current through a parasitic PN diode. CONSTITUTION: A PIN diode(10) is provided with a GaAs substrate(11), a low temperature GaAs buffer layer(18) formed at the upper portion of the GaAs substrate by carrying out a molecular beam epitaxial process at a predetermined low temperature, and an N-type GaAs layer(13) formed at the upper portion of the low temperature GaAs buffer layer. The pin diode further includes I-type GaAs layer(14) formed at the predetermined upper portion of the N-type GaAs layer, a P-type GaAs layer(15) formed at the upper portion of the I-type GaAs layer, a P-type metal(16) formed on the P-type GaAs layer, and an N-type metal(17) formed on the predetermined portion of the N-type GaAs layer.

Abstract translation: 目的：提供一种PIN二极管及其制造方法，能够降低通过寄生PN二极管的泄漏电流。 本发明公开了一种PIN二极管（10），包括GaAs衬底（11），通过在预定的低温下进行分子束外延工艺在GaAs衬底的上部形成的低温GaAs缓冲层（18） 和形成在低温GaAs缓冲层上部的N型GaAs层（13）。 PIN二极管还包括形成在N型GaAs层的预定上部处的I型GaAs层（14），形成在I型GaAs层的上部处的P型GaAs层（15）， 形成在P型GaAs层上的P型金属（16）和形成在N型GaAs层的预定部分上的N型金属（17）。

公开(公告)号：KR1020030085379A

公开(公告)日：2003-11-05

申请号：KR1020020023784

申请日：2002-04-30

Applicant: 국방과학연구소

Inventor： 정명득 ,  우병일 ,  정해원 ,  김종명 ,  김기철

IPC: H01L29/868

Abstract: PURPOSE: A PIN diode and a method for manufacturing the same are provided to be capable of reducing the leakage current through a parasitic PN diode. CONSTITUTION: A PIN diode(10) is provided with a GaAs substrate(11), a low temperature GaAs buffer layer(18) formed at the upper portion of the GaAs substrate by carrying out a molecular beam epitaxial process at a predetermined low temperature, and an N-type GaAs layer(13) formed at the upper portion of the low temperature GaAs buffer layer. The pin diode further includes I-type GaAs layer(14) formed at the predetermined upper portion of the N-type GaAs layer, a P-type GaAs layer(15) formed at the upper portion of the I-type GaAs layer, a P-type metal(16) formed on the P-type GaAs layer, and an N-type metal(17) formed on the predetermined portion of the N-type GaAs layer.

Abstract translation: 目的：提供PIN二极管及其制造方法以能够减少通过寄生PN二极管的漏电流。 构成：PIN二极管（10）具有GaAs衬底（11），通过在预定的低温下进行分子束外延工艺而形成在GaAs衬底的上部的低温GaAs缓冲层（18） 和形成在低温GaAs缓冲层的上部的N型GaAs层（13）。 pin二极管还包括形成在N型GaAs层的预定上部的I型GaAs层（14），形成在I型GaAs层的上部的P型GaAs层（15）， 形成在P型GaAs层上的P型金属（16）和形成在N型GaAs层的预定部分上的N型金属（17）。