公开(公告)号：KR1020050004651A

公开(公告)日：2005-01-12

申请号：KR1020030044910

申请日：2003-07-03

Applicant: 삼성전자주식회사

Inventor： 김남중

IPC: H01L21/3065

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to avoid generation of a slope regardless of an etch pattern density by dry-etching a hard mask layer while using SF6 as reaction gas. CONSTITUTION: A gate oxide layer(32), a polysilicon layer(34) and a hard mask layer(36) are sequentially stacked on a semiconductor substrate(30). A photoresist pattern(38) is formed on the hard mask layer. A part of the hard mask layer is dry-etched to expose polysilicon by using the photoresist pattern as an etch mask and using SF6 as reaction gas. The hard mask layer is dry-etched in a reaction chamber in which a plasma reaction occurs.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以避免通过在使用SF6作为反应气体的情况下通过干蚀刻硬掩模层而不管蚀刻图案密度而产生斜率。 构成：半导体衬底（30）依次层叠栅极氧化物层（32），多晶硅层（34）和硬掩模层（36）。 在硬掩模层上形成光致抗蚀剂图案（38）。 通过使用光致抗蚀剂图案作为蚀刻掩模并使用SF 6作为反应气体，干蚀刻硬掩模层的一部分以暴露多晶硅。 在其中发生等离子体反应的反应室中干蚀刻硬掩模层。

公开(公告)号：KR1020010009776A

公开(公告)日：2001-02-05

申请号：KR1019990028352

申请日：1999-07-14

Applicant: 삼성전자주식회사

Inventor： 김홍일 ,  김남중 ,  김영희

IPC: H01L21/027

Abstract: PURPOSE: A semiconductor device having a fine gap between patterns and a method for forming the same are provided to easily form a fine gap by applying another fabrication technique to a present light-exposing step, and ensure a maximum pattern area. CONSTITUTION: A spacer is formed on a pattern sidewall made of a specific material by a common light-exposing method. The spacer is made of the same material as the specific material, thereby reducing a gap between patterns. The gap is formed to have 0.1 micrometer or below. The pattern is a floating gate pattern of a flash memory.

Abstract translation: 目的：提供一种在图案之间具有微小间隙的半导体器件及其形成方法，通过对本发明的曝光步骤应用另一制造技术来容易地形成精细间隙，并确保最大图案面积。 构成：通过普通的曝光方法在由特定材料制成的图案侧壁上形成间隔物。 间隔件由与特定材料相同的材料制成，从而减小图案之间的间隙。 间隙形成为0.1微米或更小。 该图案是闪存的浮动栅格图案。

公开(公告)号：KR1020000072964A

公开(公告)日：2000-12-05

申请号：KR1019990015936

申请日：1999-05-03

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  김남중

IPC: H01L21/28

Abstract: PURPOSE: A method for forming a butting contact hole is provided to prevent an etching stop phenomenon by minimizing a difference of an etch rate between a center and an edge of a wafer. CONSTITUTION: A lower conductive layer is formed on a semiconductor substrate. An insulating layer is formed on the lower conductive layer, including an intermediate conductive layer overlapping an upper part of the lower conductive layer. A butting contact hole is formed by etching the insulating layer. For an etching gas CO and O2 are used.

Abstract translation: 目的：提供一种用于形成对接接触孔的方法，以通过最小化晶片的中心和边缘之间的蚀刻速率的差异来防止蚀刻停止现象。 构成：在半导体衬底上形成下导电层。 绝缘层形成在下导电层上，包括与下导电层的上部重叠的中间导电层。 通过蚀刻绝缘层形成对接接触孔。 对于蚀刻气体使用CO和O 2。

公开(公告)号：KR1020000041362A

公开(公告)日：2000-07-15

申请号：KR1019980057221

申请日：1998-12-22

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  윤석훈 ,  정민제 ,  김홍일 ,  이형규 ,  김남중

IPC: H01L21/265

Abstract: PURPOSE: A method of manufacturing a semiconductor device is to preclude the difference of an etch rate due to the difference of a pattern density, namely a loading effect, form being generated. CONSTITUTION: A method of manufacturing a semiconductor device, in which a prescribed film formed within an area(105) with high pattern density and an area(106) with low pattern density is etched, comprises the steps of: ion-implanting an impurity ion in an area having relative low etch rate against the prescribed film among the area with high pattern density and the area with low pattern density; forming an etching mask on the prescribed film and the ion-implanted film; etching simultaneously the prescribed film and the ion-implanted film using the etching mask to form a pattern(102a,103a); and removing the etching mask.

Abstract translation: 目的：一种制造半导体器件的方法是排除由于图案密度的不同而引起的蚀刻速率的差异，即形成的负载效应。 构成：一种制造半导体器件的方法，其中蚀刻形成在具有高图案密度的区域（105）内的规定膜和具有低图案密度的区域（106）的半导体器件包括以下步骤：离子注入杂质离子 在具有高图案密度的区域和具有低图案密度的区域中相对于规定膜具有相对低的蚀刻速率的区域; 在规定的膜和离子注入膜上形成蚀刻掩模; 使用蚀刻掩模同时蚀刻规定的膜和离子注入膜以形成图案（102a，103a）; 并去除蚀刻掩模。

公开(公告)号：KR1020000030956A

公开(公告)日：2000-06-05

申请号：KR1019980044411

申请日：1998-10-22

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  김남중 ,  김홍일 ,  정민제 ,  박재현

IPC: H01L21/306

Abstract: PURPOSE: A method for etching a polysilicon for forming a gate electrode is provided to reduce a tail generated in a bottom part of the gate electrode and to obtain a vertical profile by increasing an out gassing effect according to the reduction of the pattern size. CONSTITUTION: A preventing film of reflection and a polysilicon film are successively etched in an etching chamber by using a photoresist film as a mask. Herein, a certain thickness of the polysilicon film is etched by using 10-100sccm of Cl2 gas, 20-60sccm of SF6 gas, 20-200sccm CF4 gas, or 0-20sccm of HeO2 gas in a pressure for 20-100mTorr and a power for 150-400W. And then, the remained polysilicon film is etched by using 10-100sccm of Cl2 gas and 30-150sccm of HBr gas in the pressure for 75-200mTorr and the power for 50-300W to form a gate electrode(104a). Herein, the side of a top part(B) is 230mm, and the size of a bottom part(A) is 250mm. Therefore, a tail generated in the bottom part of the gate electrode and a polymer are reduced while obtaining a vertical profile.

Abstract translation: 目的：提供一种用于蚀刻用于形成栅电极的多晶硅的方法，以减少在栅电极的底部产生的尾部，并且通过根据图案尺寸的减小增加放气效果来获得垂直轮廓。 构成：通过使用光致抗蚀剂膜作为掩模，在蚀刻室中连续蚀刻防反射膜和多晶硅膜。 这里，通过使用10-100sccm的Cl 2气体，20-60sccm的SF 6气体，20-200sccm的CF 4气体或者0〜20sccm的HeO 2气体在20-100mTorr的压力下蚀刻多晶硅膜的一定厚度， 150-400W。 然后，通过使用10-100sccm的Cl 2气体和在压力为75-200mTorr的30-150sccm的HBr气体蚀刻剩余的多晶硅膜，并且为50-300W的功率蚀刻形成栅电极（104a）。 这里，顶部（B）的一侧为230mm，底部（A）的尺寸为250mm。 因此，在栅电极的底部和聚合物中产生的尾部减少，同时获得垂直轮廓。