公开(公告)号：KR1020050011060A

公开(公告)日：2005-01-29

申请号：KR1020030049899

申请日：2003-07-21

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  정민제

IPC: H01L21/28

Abstract: PURPOSE: A method of manufacturing a semiconductor device with contact holes for metal lines is provided to reduce manufacturing time and fabrication costs by forming the contact holes using in-situ processing under a carbon-rich process gas atmosphere. CONSTITUTION: An etch stop layer(140) and predetermined layers(143,146) are sequentially formed on a semiconductor substrate(100) with buried contact plugs(136). A plurality of contact holes(158) for exposing the buried contact plugs to the outside are formed in the resultant structure by etching sequentially the predetermined layers and the etch stop layer using in-situ processing under a carbon-rich process gas condition.

Abstract translation: 目的：提供一种制造具有用于金属线的接触孔的半导体器件的方法，以通过在富碳工艺气体气氛下使用原位处理形成接触孔来减少制造时间和制造成本。 构成：在具有埋入式接触塞（136）的半导体衬底（100）上依次形成蚀刻停止层（140）和预定层（143,146）。 通过在富碳处理气体条件下使用原位处理依次蚀刻预定层和蚀刻停止层，在所得到的结构中形成用于将埋入的接触塞暴露于外部的多个接触孔（158）。

公开(公告)号：KR1020000027241A

公开(公告)日：2000-05-15

申请号：KR1019980045137

申请日：1998-10-27

Applicant: 삼성전자주식회사

Inventor： 이윤영 ,  석종욱 ,  정민제

IPC: H01L21/28

Abstract: PURPOSE: A metal wire formation method is provided to easily secure an anti-corrosion margin by easily removing remained polymer and Cl using plasma etching including etching gas contained fluorine(F). CONSTITUTION: A metal film, such as aluminum(Al) or tungsten(W) is formed on an insulating layer(100), and then a metal pattern(104) used for metal wires is formed by etching the metal film using a photoresist pattern(106) as a mask. A polymer(108) is simultaneously formed at both sides of the metal pattern(104). By using plasma etching gas contained fluorine(F), the polymer(108) is etched. Then, the remained polymer(108) and the photoresist pattern(106) are removed by asking process.

Abstract translation: 目的：提供一种金属线形成方法，通过容易地除去残留的聚合物和Cl，使用含有氟（F）的蚀刻气体的等离子体蚀刻来容易地确保防腐蚀边缘。 构成：在绝缘层（100）上形成诸如铝（Al）或钨（W）的金属膜，然后通过使用光致抗蚀剂图案蚀刻金属膜来形成用于金属线的金属图案（104） （106）作为掩模。 聚合物（108）同时形成在金属图案（104）的两侧。 通过使用包含氟（F）的等离子体蚀刻气体，蚀刻聚合物（108）。 然后，通过询问处理除去残留的聚合物（108）和光刻胶图案（106）。

公开(公告)号：KR1019970077073A

公开(公告)日：1997-12-12

申请号：KR1019960016211

申请日：1996-05-15

Applicant: 삼성전자주식회사

Inventor： 정민제

IPC: H01L21/00

Abstract: 반도체 소자 제조장치별로 웨이퍼를 이송하는 캐리어 및 캐리어 이송박스에 흡착되어 있는 불순물에 의한 웨이퍼의 오염을 방지하는 반도체 제조공정의 웨이퍼 오염방지 방법에 관한 것이다.
본 발명은, 캐리어 및 캐리어 이송박스에 웨이퍼를 실어서 반도체 소자 공정별 장치로의 이송이 이루어지는 반도체 제조 공정에 있어서, 상기 캐리어 및 캐리어 이송박스를 금속공정후 오염되지 않은 것으로 교체시킴을 구비하여 이루어진다.
따라서, 웨이퍼가 오염되는 것을 방지할 수 있다는 효과가 있다.

公开(公告)号：KR1020020028457A

公开(公告)日：2002-04-17

申请号：KR1020000059480

申请日：2000-10-10

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  정민제

IPC: H01L21/3065

Abstract: PURPOSE: A method for dry-etching a semiconductor device is provided to minimize particles generated on a wafer where an etch process is performed, by making radio frequency(RF) power not turn off until a dry etch process is completed. CONSTITUTION: A semiconductor wafer having a multilayer is transferred to an etch chamber. A predetermined portion of an uppermost layer of the multilayer is etched to form an opening. A stabilization process is performed regarding a chamber while RF power is applied to the etch chamber. A lower layer exposed to a lower portion by the opening is over-etched.

Abstract translation: 目的：提供一种用于干法蚀刻半导体器件的方法，以通过使射频（RF）功率不被关闭直到干法蚀刻工艺完成来最小化在执行蚀刻工艺的晶片上产生的颗粒。 构成：将具有多层的半导体晶片转移到蚀刻室。 蚀刻多层的最上层的预定部分以形成开口。 在将RF功率施加到蚀刻室的同时对室进行稳定处理。 通过开口暴露于下部的下层被过度蚀刻。

公开(公告)号：KR1020010038609A

公开(公告)日：2001-05-15

申请号：KR1019990046654

申请日：1999-10-26

Applicant: 삼성전자주식회사

Inventor： 조상연 ,  정민제

IPC: H01L21/76

Abstract: PURPOSE: A field isolation method for a flash memory device is provided to easily compensate for a dent phenomenon when a field isolation process is performed by using a shallow trench isolation(STI) method. CONSTITUTION: A polysilicon layer(17) is stacked on a silicon substrate(10) having a native oxide layer, and a silicon nitride layer(13) for patterning is stacked and patterned. The polysilicon layer and a silicon layer of the substrate in a region where the silicon nitride is removed by the patterning process, are sequentially etched to form an empty trench of predetermined width and depth by using the silicon nitride layer as an etching mask. A silicon oxide layer(11) and a silicon nitride layer for buffering are formed inside the empty trench. A silicon oxide layer for isolation is deposited by a chemical vapor deposition(CVD) process. The silicon oxide layer for isolation stacked on the silicon nitride layer for patterning is eliminated by a chemical mechanical polishing(CMP) process. The silicon nitride layer for patterning is eliminated. An insulating layer for filling a dent formed by the silicon nitride layer for buffering when the silicon nitride layer for patterning is eliminated, is stacked on the entire substrate, and an etching process is entirely performed.

Abstract translation: 目的：提供一种用于闪存器件的场隔离方法，以便通过使用浅沟槽隔离（STI）方法来执行场隔离处理时容易地补偿凹陷现象。 构成：在具有天然氧化物层的硅衬底（10）上层叠多晶硅层（17），并且层叠图案化用于图案化的氮化硅层（13）。 通过使用氮化硅层作为蚀刻掩模，依次蚀刻在通过图案化工艺去除氮化硅的区域中的多晶硅层和衬底的硅层以形成预定宽度和深度的空沟槽。 在空槽内部形成氧化硅层（11）和用于缓冲的氮化硅层。 通过化学气相沉积（CVD）工艺沉积用于隔离的氧化硅层。 通过化学机械抛光（CMP）工艺消除叠层在用于图案化的氮化硅层上的用于隔离的氧化硅层。 消除用于图案化的氮化硅层。 当排除用于图案化的氮化硅层时用于填充由氮化硅层形成的用于缓冲的凹陷的绝缘层堆叠在整个衬底上，并且完全进行蚀刻工艺。

公开(公告)号：KR1020010037574A

公开(公告)日：2001-05-15

申请号：KR1019990045158

申请日：1999-10-18

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  성광제

IPC: H01L27/11

Abstract: PURPOSE: A method for forming a load resistance of an SRAM cell is to prevent a photoresist remainder from being generated in ashing and strip processes. CONSTITUTION: An interlayer dielectric(102) is deposited on a semiconductor substrate(100). A semiconductor layer is formed on the interlayer dielectric. The first photoresist pattern is formed on the semiconductor layer. The first photoresist pattern serves for masking a region where a load resistance(R) is formed thereon. An impurity ion is implanted into the exposed region of the semiconductor layer, using the first photoresist pattern as a mask. The first photoresist pattern is removed from the semiconductor layer. The second photoresist pattern is formed on the semiconductor layer. The second photoresist pattern serves for defining a load resistance pattern. After patterning the semiconductor layer, using the second photoresist pattern as a mask, the load resistance, a power supply line(115), and a node is formed by removing the second photoresist pattern, using ashing and strip processes.

Abstract translation: 目的：形成SRAM单元的负载电阻的方法是防止在灰化和剥离过程中产生光致抗蚀剂剩余部分。 构成：层间电介质（102）沉积在半导体衬底（100）上。 在层间电介质上形成半导体层。 第一光致抗蚀剂图案形成在半导体层上。 第一光致抗蚀剂图形用于掩蔽在其上形成负载电阻（R）的区域。 使用第一光致抗蚀剂图案作为掩模将杂质离子注入到半导体层的曝光区域中。 从半导体层去除第一光致抗蚀剂图案。 第二光致抗蚀剂图案形成在半导体层上。 第二光致抗蚀剂图案用于限定负载电阻图案。 在图案化半导体层之后，使用第二光致抗蚀剂图案作为掩模，通过使用灰化和剥离处理去除第二光致抗蚀剂图案来形成负载电阻，电源线（115）和节点。

公开(公告)号：KR1020000061306A

公开(公告)日：2000-10-16

申请号：KR1019990010256

申请日：1999-03-25

Applicant: 삼성전자주식회사

Inventor： 정민제 ,  백재학 ,  김태룡

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a metal fuse of a semiconductor device is provided to decrease or minimize a defect of a metal fuse by completely eliminating a horn-type passivation oxidation layer. CONSTITUTION: A method for manufacturing a metal fuse of a semiconductor device comprises the steps of: forming a passivation layer(40) covering a metal layer formed on a barrier metal layer(20) to be used for a fuse, and forming a photoresist pattern exposing a part of the passivation layer; anisotropically etching a predetermined thickness of the passivation layer by using the photoresist pattern as an etch mask, and etching the exposed metal layer by a predetermined thickness; and anisotropically etching a predetermined thickness of the passivation layer again by using the etch mask, and repeatedly etching the exposed metal layer by a predetermined thickness, so that the metal layer and the passivation layer are completely etched and the barrier metal layer remains as the fuse.

Abstract translation: 目的：提供一种用于制造半导体器件的金属熔丝的方法，以通过完全消除喇叭型钝化氧化层来减少或最小化金属熔丝的缺陷。 构成：用于制造半导体器件的金属熔丝的方法包括以下步骤：形成覆盖形成在用于保险丝的阻挡金属层（20）上的金属层的钝化层（40），并形成光致抗蚀剂图案 暴露一部分钝化层; 通过使用光致抗蚀剂图案作为蚀刻掩模，各向异性蚀刻钝化层的预定厚度，并将暴露的金属层蚀刻预定厚度; 并通过使用蚀刻掩模再次蚀刻预定厚度的钝化层，并且将暴露的金属层重复蚀刻预定厚度，使得金属层和钝化层被完全蚀刻，并且阻挡金属层保持为保险丝 。

公开(公告)号：KR1020000021053A

公开(公告)日：2000-04-15

申请号：KR1019980039974

申请日：1998-09-25

Applicant: 삼성전자주식회사

Inventor： 이재봉 ,  서정근 ,  이현철 ,  정민제

IPC: H01L21/28

Abstract: PURPOSE: A method of forming a metal wiring of a semiconductor device is provided to prevent a by-product from being generated when a contact hole is formed, and to prevent the corrosion of an aluminum film when the aluminum film is exposed in the atmosphere. CONSTITUTION: A barrier layer(102), an aluminum layer(104), and a capping layer(106) are in order formed in a first inter layer insulated film(100). The barrier layer is made of one selected from a Ti film or a Ti/TiN, and the capping layer is made of TiN film. A tungsten layer(108) is formed on the capping layer as a meal film. The tungsten film has a thin thickness relative to that of the aluminum film. A photoresist film pattern(110) is formed on the tungsten film. The tungsten film is etched by using the pattern as a mask.

Abstract translation: 目的：提供一种形成半导体器件的金属布线的方法，以防止在形成接触孔时副产物产生，并且防止当铝膜暴露于大气中时铝膜的腐蚀。 构成：在第一层间绝缘膜（100）中依次形成阻挡层（102），铝层（104）和覆盖层（106）。 阻挡层由选自Ti膜或Ti / TiN中的一种制成，并且覆盖层由TiN膜制成。 在覆盖层上形成作为餐膜的钨层（108）。 钨膜相对于铝膜的厚度薄。 光致抗蚀剂膜图案（110）形成在钨膜上。 通过使用图案作为掩模来蚀刻钨膜。

公开(公告)号：KR100147599B1

公开(公告)日：1998-11-02

申请号：KR1019940021083

申请日：1994-08-25

Applicant: 삼성전자주식회사

Inventor： 문대식 ,  곽규환 ,  정민제

IPC: H01L21/302

Abstract: 신규한 이방성 건식식각 방법이 개시되어 있다. 상층막과 하층막으로 구성되는 다층막을 이방성 식각하는 반도체장치의 제조방법에 있어서, 평행평판형 시스템에서 브로모수소(HBr)가스, 육불화황(SF
6 )가스, 산소(O
2 )가스 및 염소(C1
2 )가스를 혼합하여 상기 상층막을 이방성 식각한다. 수직 프로파일을 얻을 수 있고, 마이크로 로딩 효과를 감소시킬 수 있다.

公开(公告)号：KR1019970052397A

公开(公告)日：1997-07-29

申请号：KR1019950059335

申请日：1995-12-27

Applicant: 삼성전자주식회사

Inventor： 한준호 ,  정민제

IPC: H01L21/28

Abstract: 본 발명은 건식 식각 공정에 의한 콘택 홀의 형성과 동시에 콘택 홀 부위에 노출된 반도체 기판상에 실리콘 처리를 하므로써, 반도체 장치의 제조 공정을 단순화한 반도체 장치의 제조 방법에 관한 것이다. 특히, 반응가스로서 O
2 /CF
4 가스를 사용하여 콘택홀을 형성하기 위한 식각 공정과 콘택 홀 부위의 반도체 기판상에 실리콘 처리하는 공정을 하나의 공정에서 실시하므로써, 공정 단순화 및 반도체 장치의 수율 및 품질을 향상시킬 수 있게 된다.