公开(公告)号：KR1020050072316A

公开(公告)日：2005-07-11

申请号：KR1020040000707

申请日：2004-01-06

Applicant: 삼성전자주식회사

Inventor： 김남중 ,  김무현

IPC: H01L21/336

CPC classification number: H01L21/823437 ,  H01L21/28035 ,  H01L21/3065

Abstract: 폴리실리콘으로 이루어지는 게이트 패턴 형성 방법이 개시되어 있다. 식각 챔버 내에 불소를 포함하는 가스 및 폴리실리콘막 식각용 가스를 제공하여 폴리실리콘막의 측면에 보호용 폴리머를 생성하면서 상기 폴리실리콘막을 부분적으로(partially) 1차 식각한다. 상기 식각 챔버 내에 남아있는 불소 라디컬을 식각 챔버 외부로 펌핑한다. 이어서, 상기 식각 챔버 내에 폴리실리콘막 식각용 가스를 제공하여 상기 게이트 산화막이 노출되도록 상기 폴리실리콘막을 2차 식각한다. 상기 공정에 의하면 패턴 형성시에 하부막의 피팅 불량 등을 최소화할 수 있다.

公开(公告)号：KR1020020009190A

公开(公告)日：2002-02-01

申请号：KR1020000042693

申请日：2000-07-25

Applicant: 삼성전자주식회사

Inventor： 김남중 ,  이현철

IPC: H01L21/306

Abstract: PURPOSE: An etch apparatus for fabricating a semiconductor is provided to compensate easily a temperature of a reaction chamber by using an end point detector window connected with a cable of a detector. CONSTITUTION: A heating portion(30) is installed in an end point detector window(12). The end point detector window(12) is connected with a cable(18) of a detector. The heating portion(30) is used for compensating a temperature in an etch process of a reaction chamber(10). The heating portion(30) has a heating line. The heating line of the heating portion(30) is wound between the end point detector window(12) and a housing(25) for forming a peripheral region of the end point detector window(12). A power supply portion is used for supplying power to the heating line. A control portion is connected with the power supply portion. The control portion is used for controlling the power supply portion and monitoring an internal temperature of the reaction chamber(10).

Abstract translation: 目的：提供一种用于制造半导体的蚀刻装置，通过使用与检测器的电缆连接的端点检测器窗口来容易地补偿反应室的温度。 构成：加热部分（30）安装在端点检测器窗口（12）中。 端点检测器窗口（12）与检测器的电缆（18）连接。 加热部分（30）用于补偿反应室（10）的蚀刻工艺中的温度。 加热部（30）具有加热线。 加热部分（30）的加热线缠绕在端点检测器窗口（12）和用于形成端点检测器窗口（12）的周边区域的壳体（25）之间。 供电部分用于向加热线供电。 控制部与电源部连接。 控制部分用于控制供电部分并监测反应室（10）的内部温度。

公开(公告)号：KR1020010055526A

公开(公告)日：2001-07-04

申请号：KR1019990056742

申请日：1999-12-10

Applicant: 삼성전자주식회사

Inventor： 박재현 ,  김남중 ,  김홍일 ,  고동환

IPC: H01L27/115

Abstract: PURPOSE: A method for etching gate of non-volatile memory device is provided to prevent an inferiority due to a residue of electric conduction layer a degradation of a device by, preventing generation of fitting on a surface of a substrate while realizing a vertical profile of a gate, and minimizing the loss of a field oxide layer. CONSTITUTION: A field oxide layer(101) is formed on a semiconductor substrate(100) to separate the semiconductor substrate(100) into to an active area and a field area. A tunnel oxide layer(102), a floating gate layer(104), interlayer dielectric layer(106), a control gate layer(110), and a capping layer(112) are sequentially formed on the substrate(100). A photoresist film pattern(114) is formed on the top of the capping layer(112). The photoresist film pattern(114) is used as a mask to etch the capping layer(112). The photoresist film pattern(114) is used as the mask to sequentially etch the control gate layer(110), the interlayer dielectric layer(106) and the floating gate layer(104). The floating gate layer(104) is etched in an oxygen-system gas atmosphere.

Abstract translation: 目的：提供一种用于蚀刻非易失性存储器件的栅极的方法，以防止由于导电层残留导致器件劣化的劣化，从而防止在衬底的表面上产生拟合，同时实现垂直形状 栅极，并使场氧化物层的损耗最小化。 构成：在半导体基板（100）上形成场氧化物层（101），以将半导体衬底（100）分离成有源区域和场区域。 在衬底（100）上依次形成隧道氧化物层（102），浮栅层（104），层间电介质层（106），控制栅极层（110）和覆盖层（112）。 在覆盖层（112）的顶部上形成光致抗蚀剂膜图案（114）。 光致抗蚀剂膜图案（114）用作掩模以蚀刻封盖层（112）。 光致抗蚀剂膜图案（114）用作掩模以顺序蚀刻控制栅极层（110），层间介电层（106）和浮栅层（104）。 在氧系气体气氛中蚀刻浮栅层（104）。

公开(公告)号：KR1020040057496A

公开(公告)日：2004-07-02

申请号：KR1020020084246

申请日：2002-12-26

Applicant: 삼성전자주식회사

Inventor： 김남중

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a semiconductor device having a tungsten silicide line pattern is provided to prevent a not-open defect from being generated on the tungsten silicide line pattern by effectively controlling the thickness of an anti-reflective coating before the post process for forming a contact hole. CONSTITUTION: A tungsten silicide layer(124) is formed on a semiconductor substrate(100). The first anti-reflective coating pattern having the first thickness is formed on the resultant structure for partially exposing the tungsten silicide layer. The second anti-reflective coating pattern(130b) having the second thickness is formed by carrying out the first etching process on the resultant structure using the first etching gas(150). The first etching gas has a higher etching rate for the anti-reflective coating pattern than the tungsten silicide layer. A metal line pattern is completed by carrying out the second etching process on the resultant structure using the second etching gas having a higher etching rate for the tungsten silicide layer than the anti-reflective coating pattern. At this time, the third anti-reflective coating pattern having the third thickness is formed on the metal line pattern.

Abstract translation: 目的：提供一种制造具有硅化钨线图案的半导体器件的方法，以通过在形成后处理之后有效地控制抗反射涂层的厚度来防止在硅化钨线图案上产生不开放的缺陷 一个接触孔。 构成：在半导体衬底（100）上形成硅化钨层（124）。 在所得结构上形成具有第一厚度的第一抗反射涂层图案，以部分地暴露硅化钨层。 具有第二厚度的第二抗反射涂层图案（130b）通过使用第一蚀刻气体（150）对所得到的结构进行第一蚀刻工艺而形成。 与硅化钨层相比，第一蚀刻气体具有比抗反射涂层图案更高的蚀刻速率。 通过使用对于硅化钨层具有比抗反射涂层图案更高的蚀刻速率的第二蚀刻气体对所得到的结构进行第二蚀刻处理来完成金属线图案。 此时，在金属线图案上形成具有第三厚度的第三抗反射涂层图案。

公开(公告)号：KR1020010097278A

公开(公告)日：2001-11-08

申请号：KR1020000021225

申请日：2000-04-21

Applicant: 삼성전자주식회사

Inventor： 김남중

IPC: H01L21/66

Abstract: 본 발명은 반도체 웨이퍼의 불량 여부를 검사하기 위한 반도체 웨이퍼 검사 장치에 관한 것이다. 반도체 웨이퍼 검사 장치는 반도체 웨이퍼가 적재된 캐리어가 놓여지는 검사용 캐리어 지지대, 반도체 웨이퍼를 검사하기 위한 현미경 측정부, 불량 반도체 웨이퍼를 담기 위한 빈 캐리어가 놓여지는 불량용 캐리어 지지대, 반도체 웨이퍼를 이동시키는 로봇 아암 및 로봇 아암을 제어하기 위한 제어부를 포함한다. 검사용 캐리어 내의 반도체 웨이퍼는 제어부에 의해 선택적으로 현미경 측정부 또는 빈 캐리어로 이동될 수 있다. 따라서, 검사 결과 불량 웨이퍼가 발생할 경우에는 현미경에 의한 검사가 종료되어 검사용 캐리어로 재로딩된 불량 웨이퍼를 빈 캐리어로 분리시킬 수 있게 된다.

公开(公告)号：KR1020080034601A

公开(公告)日：2008-04-22

申请号：KR1020060100760

申请日：2006-10-17

Applicant: 삼성전자주식회사

Inventor： 김남중 ,  박재현

IPC: H01L21/336

Abstract: A method for forming a gate of a semiconductor memory device using an end pointer detecting device is provided to avoid fluctuation of a cell current by avoiding generation of undercut or fail of a gate. A gate oxide layer(202), a polysilicon layer(204) and a tungsten silicide layer(206) are sequentially deposited on a silicon substrate(200). A mask pattern is formed on the tungsten silicide layer. While using the mask pattern as an etch mask, a point of time when the polysilicon layer is exposed is set as an end pointer by using etchant having good etch selectivity with respect to an oxide layer and a high etch rate with respect to tungsten silicide so that a main etch process is performed on the tungsten silicide layer. A predetermined thickness of the polysilicon layer is over-etched by using etchant having good etch selectivity with respect to an oxide layer and a high etch rate with respect to polysilicon. While using etchant having good etch selectivity with respect to an oxide layer and a high etch rate with respect to polysilicon, a point of time when the oxide layer is exposed is set as an end pointer to perform a main etch process on the polysilicon layer. The polysilicon layer is over-etched by using etchant having good etch selectivity with respect to an oxide layer and a high etch rate with respect to polysilicon. The etchant used in etching the tungsten silicide layer and the polysilicon layer can be SF6/Cl2.

Abstract translation: 提供一种使用端指针检测装置形成半导体存储器件的栅极的方法，以避免产生栅极的底切或失败的电池电流的波动。 栅极氧化物层（202），多晶硅层（204）和硅化钨层（206）依次沉积在硅衬底（200）上。 在硅化钨层上形成掩模图案。 当使用掩模图案作为蚀刻掩模时，通过使用相对于氧化物层具有良好蚀刻选择性的蚀刻剂和相对于硅化钨的高蚀刻速率，将多晶硅层暴露的时间点设置为终点指针 在硅化钨层上进行主蚀刻工艺。 通过使用相对于氧化物层具有良好蚀刻选择性的蚀刻剂和相对于多晶硅的高蚀刻速率来蚀刻多晶硅层的预定厚度。 虽然使用相对于氧化物层具有良好蚀刻选择性的蚀刻剂和相对于多晶硅的高蚀刻速率，但是将氧化物层暴露的时间点设置为端指针，以对多晶硅层执行主蚀刻工艺。 通过使用相对于氧化物层具有良好蚀刻选择性的蚀刻剂和相对于多晶硅的高蚀刻速率，多晶硅层被过度蚀刻。 用于蚀刻硅化钨层和多晶硅层的蚀刻剂可以是SF6 / Cl2。

公开(公告)号：KR1020030090180A

公开(公告)日：2003-11-28

申请号：KR1020020028185

申请日：2002-05-21

Applicant: 삼성전자주식회사

Inventor： 김남중

IPC: H01L21/68

Abstract: PURPOSE: A semiconductor fabrication apparatus including a wafer flat zone aligner is provided to reduce an error rate by using the wafer flat zone aligner to align a flat zone of a wafer. CONSTITUTION: A semiconductor fabrication apparatus including a wafer flat zone aligner includes a door(110), a loading portion(120), and one or more process chambers. A reception groove(112) is formed at a predetermined position of an upper portion of the door(110) opposite to an opening portion of a cassette. A loading groove(114) is formed at the predetermined position of the upper portion of the door(110) opposite to a support bar of the cassette. An up/down portion(250) is installed at a base of the reception groove(112). A wafer rotation unit(210) is installed at the up/down portion(250) in order to align flat zones of wafers. A plurality of opening holes(122,124) are formed at the loading portion(120) corresponding to the reception groove(112) and the loading groove(114) of the loading portion(120).

Abstract translation: 目的：提供一种包括晶片平面区域对准器的半导体制造装置，以通过使用晶片平面区域对准器来对准晶片的平坦区域来降低错误率。 构成：包括晶片平面区域对准器的半导体制造装置包括门（110），装载部分（120）和一个或多个处理室。 接收槽（112）形成在门（110）的与盒的开口部分相对的上部的预定位置处。 在门（110）的上部与盒的支撑杆相对的预定位置处形成有装载槽（114）。 上部/下部（250）安装在接收槽（112）的底部。 晶片旋转单元（210）安装在上/下部分（250）处以便对准平坦的晶片区域。 在对应于接收槽（112）和装载部分（120）的装载槽（114）的装载部分（120）处形成有多个打开孔（122,124）。

公开(公告)号：KR1020020096533A

公开(公告)日：2002-12-31

申请号：KR1020010035093

申请日：2001-06-20

Applicant: 삼성전자주식회사

Inventor： 이현철 ,  김남중

IPC: H01L21/336

Abstract: PURPOSE: A gate pattern formation method is provided to prevent an etch damage of a semiconductor substrate and to easily form a gate pattern having a vertical sidewall. CONSTITUTION: A first and a second insulating layer having different etching selectivities are sequentially formed on a semiconductor substrate(100) having an isolation layer(110). A second insulating pattern(131) and a first insulating pattern(121) are sequentially formed to expose the semiconductor substrate(100) by patterning the second and first insulating layer. A gate oxide layer is formed on the exposed semiconductor substrate(100). A gate conductive pattern(200) is formed on the gate oxide layer. Then, the second insulating pattern(131) and the first insulating pattern(121) are removed. A silicon nitride layer is used as the first insulating layer, and a silicon oxide layer is used as the second insulating layer.

Abstract translation: 目的：提供一种栅极图案形成方法，以防止半导体衬底的蚀刻损伤并且容易地形成具有垂直侧壁的栅极图案。 构成：具有不同蚀刻选择性的第一绝缘层和第二绝缘层依次形成在具有隔离层（110）的半导体衬底（100）上。 顺序地形成第二绝缘图案（131）和第一绝缘图案（121），以通过图案化第二绝缘层和第一绝缘层来露出半导体衬底（100）。 在暴露的半导体衬底（100）上形成栅氧化层。 在栅极氧化物层上形成栅极导电图案（200）。 然后，去除第二绝缘图案（131）和第一绝缘图案（121）。 使用氮化硅层作为第一绝缘层，使用氧化硅层作为第二绝缘层。

公开(公告)号：KR1020000059749A

公开(公告)日：2000-10-05

申请号：KR1019990007573

申请日：1999-03-08

Applicant: 삼성전자주식회사

Inventor： 윤석훈 ,  김홍일 ,  이형규 ,  김남중

IPC: H01L21/306

Abstract: PURPOSE: A method for etching an insulating layer is provided to improve an etching selectivity of an etch stop layer. CONSTITUTION: A method for etching an insulating layer comprises the steps of: forming an etch stop layer(108) on a semiconductor substrate(100) with a plurality of gate electrodes(106) formed thereon; forming an insulating layer on the etch stop layer; and forming a gate electrode spacer(112) by etching the insulating layer by using a mixed etching gas including a CH4/He-O2. Thereby, an etching selectivity of the etch stop layer and the insulating layer is improved. The etch stop layer is an oxide layer, and the insulating layer is a silicon nitride layer. A flow amount of the etching gas CH4 is 20 to 200 SCCM, and a flow amount of the etching gas He-O2 is 0 to 200 SCCM.

Abstract translation: 目的：提供一种蚀刻绝缘层的方法，以提高蚀刻停止层的蚀刻选择性。 构成：蚀刻绝缘层的方法包括以下步骤：在其上形成有多个栅电极（106）的半导体衬底（100）上形成蚀刻停止层（108） 在所述蚀刻停止层上形成绝缘层; 以及通过使用包括CH 4 / He-O 2的混合蚀刻气体来蚀刻绝缘层来形成栅电极间隔物（112）。 因此，蚀刻停止层和绝缘层的蚀刻选择性得到改善。 蚀刻停止层是氧化物层，绝缘层是氮化硅层。 蚀刻气体CH4的流量为20〜200SCCM，蚀刻气体He-O2的流量为0〜200SCCM。

公开(公告)号：KR1020000027251A

公开(公告)日：2000-05-15

申请号：KR1019980045147

申请日：1998-10-27

Applicant: 삼성전자주식회사

Inventor： 김남중 ,  김홍일 ,  박재현 ,  윤석훈

IPC: H01L21/02

Abstract: PURPOSE: A wafer box having a sliding type cover is provided to prevent a run accident which could happen in opening and closing the cover of the wafer box, and eliminate the need for an area occupied by the cover of the wafer box on a station in opening the cover. CONSTITUTION: In a wafer box having a wafer box body and a wafer box cover, the body has a vacant space of enough depth so that the cover can be inserted. And the cover has a groove at which both ends of the cover mashes with both side walls in the vacant space of the body and is slided to the vacant space of the body when the wafer box is open.

Abstract translation: 目的：提供具有滑动式盖的晶片盒，以防止在打开和关闭晶片盒的盖子时可能发生的运行事故，并且不需要在车站上的晶片盒盖的占用面积 打开盖子 构成：在具有晶片盒体和晶片盒盖的晶片盒中，主体具有足够深度的空间，从而可以插入盖。 并且盖具有凹槽，盖的两端与主体的空闲空间中的两个侧壁相混合，并且当晶片盒打开时被滑动到主体的空闲空间。