公开(公告)号：KR1020140070318A

公开(公告)日：2014-06-10

申请号：KR1020130037874

申请日：2013-04-08

Applicant: 삼성전자주식회사

Inventor： 김정겸 ,  송인달 ,  최정환

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/02

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C7/22 ,  G11C2207/105 ,  G11C2207/2272

Abstract: A memory module includes multiple data ports and multiple memory devices. The data ports transceive corresponding data respectively. The memory devices include memory devices of a first set belonging to at least one rank directly connected to a corresponding data port among the data ports and memory devices of a second set belonging to at least another rank connected to the data port by passing via a corresponding memory device among the memory devices of the first set. Each of the memory devices of the first set responses to at least one chip selection signals to provide magnetic data from its memory core and at least one of other data from a memory core of one of the memory devices of the second set to the data port as the corresponding data.

Abstract translation: 存储器模块包括多个数据端口和多个存储器件。 数据端口分别收发相应的数据。 存储装置包括属于至少一个等级的至少一个等级的存储装置，该至少一个等级直接连接到数据端口中的对应数据端口，以及属于至少另一个等级的第二集合的存储装置，该第二集合通过相应的 存储器件在第一组的存储器件中。 第一组的每个存储器件响应于至少一个芯片选择信号，以从其存储器核心提供磁数据，以及从第二组的存储器件之一的存储器核心到数据端口的至少一个数据 作为相应的数据。

公开(公告)号：KR1020130086887A

公开(公告)日：2013-08-05

申请号：KR1020120007981

申请日：2012-01-26

Applicant: 삼성전자주식회사

Inventor： 김정겸 ,  최정환 ,  현석훈 ,  장성진

IPC: G11C29/42 ,  G11C7/10

CPC classification number: G06F11/1048 ,  H03M13/356 ,  H03M13/3707

Abstract: PURPOSE: A memory buffer, devices including the same, and a data processing method thereof are provided to improve error detection and correction abilities by detecting and correcting errors in the memory buffer using an ECC algorithm. CONSTITUTION: An ECC algorithm selector selects one of ECC algorithms. An ECC logic circuit (530) generates ECC data by using the selected ECC algorithm. A first selector (521) transmits first data outputted from the outside to the ECC logic circuit or transmits first ECC data outputted from the ECC logic circuit to the outside in response to a selection signal. A second selector (523) transmits second ECC data outputted from the ECC logic circuit to a semiconductor memory device or transmits second data inputted from the semiconductor memory device to the ECC logic circuit in response to the selection signal.

Abstract translation: 目的：提供存储器缓冲器，包括其的装置及其数据处理方法，以通过使用ECC算法检测和校正存储器缓冲器中的错误来提高错误检测和校正能力。 构成：ECC算法选择器选择ECC算法之一。 ECC逻辑电路（530）通过使用选择的ECC算法生成ECC数据。 第一选择器（521）将从外部输出的第一数据发送到ECC逻辑电路，或者响应于选择信号将从ECC逻辑电路输出的第一ECC数据发送到外部。 第二选择器（523）将从ECC逻辑电路输出的第二ECC数据发送到半导体存储器件，或者响应于选择信号将从半导体存储器件输入的第二数据发送到ECC逻辑电路。