公开(公告)号：KR1020090124291A

公开(公告)日：2009-12-03

申请号：KR1020080050413

申请日：2008-05-29

Applicant: 삼성전자주식회사

Inventor： 오동연 ,  송재혁

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/02

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483

Abstract: PURPOSE: A non-volatile memory device and a programming method thereof are provided to improve a program speed by selectively using a self boosting mode according to a location of a selected word line. CONSTITUTION: A memory cell array(110) includes a plurality of memory blocks. A page buffer circuit(120) stores data in memory cells according to control of a control circuit(180). A high voltage generating circuit(130) generates high voltage necessary to write and read data onto and from a memory device according to the control of the control circuit. A row selection circuit(140) performs a decoding function, a word line selection function, and function of applying voltage corresponding to word lines. A column selecting circuit(150) performs a decoding function, a bit line selection function, and a function of outputting voltage corresponding to bit lines. A data input/output circuit(160) is controlled by the control circuit. A pass/fail check circuit(170) outputs pass/fail signals to the control circuit. The control circuit controls the overall operation of a non-volatile memory device.

Abstract translation: 目的：提供一种非易失性存储器件及其编程方法，以通过根据所选字线的位置选择性地使用自增强模式来提高编程速度。 构成：存储单元阵列（110）包括多个存储块。 页面缓冲电路（120）根据控制电路（180）的控制将数据存储在存储单元中。 根据控制电路的控制，高电压产生电路（130）产生向存储器件写入和读取数据所需的高电压。 行选择电路（140）执行解码功能，字线选择功能和施加与字线对应的电压的功能。 列选择电路（150）执行解码功能，位线选择功能以及输出与位线对应的电压的功能。 数据输入/输出电路（160）由控制电路控制。 通过/失败检查电路（170）将通过/失败信号输出到控制电路。 控制电路控制非易失性存储器件的整体操作。

公开(公告)号：KR1020080030849A

公开(公告)日：2008-04-07

申请号：KR1020060097321

申请日：2006-10-02

Applicant: 삼성전자주식회사

Inventor： 이창섭 ,  최정혁 ,  이운경 ,  송재혁 ,  오동연

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L21/28273 ,  H01L21/76897 ,  H01L27/2436 ,  H01L27/2463

Abstract: A semiconductor memory device and a method for manufacturing the same are provided to reduce coupling disturbance being generated between adjacent cells when a programming operation is performed by arranging bit lines in a memory block in the order of even/even/odd/odd bit lines. Select transistors and cell transistors are formed on a semiconductor substrate(101). Bit lines are formed on the selective transistors and the cell transistors. The bit lines are electrically to the selective transistors. The bit lines are formed in at least two heights. The bit lines are configured with a pair of even bit lines(131E_1,131E_2) having first and second heights, and a pair of odd bit lines(1310_1,1310_2) having third and fourth heights. The pair of even bit lines and the pair of odd bit lines are alternatively arranged. The first height is same with the third height and the second height is same with the fourth height.

Abstract translation: 提供一种半导体存储器件及其制造方法，用于通过以偶数/偶数/奇数/奇数位线的顺序排列存储器块中的位线来执行编程操作时，减少相邻单元之间产生的耦合干扰。 选择晶体管和单元晶体管形成在半导体衬底（101）上。 位线形成在选择性晶体管和单元晶体管上。 位线与选择性晶体管电连接。 位线至少形成两个高度。 位线配置有具有第一和第二高度的一对偶数位线（131E_1,131E_2）和具有第三和第四高度的一对奇数位线（1310_1,1310_2）。 交替地布置了该对偶数位线和一对奇数位线。 第一高度与第三高度相同，第二高度与第四高度相同。