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公开(公告)号：KR100816755B1
公开(公告)日：2008-03-25
申请号：KR1020060101949
申请日：2006-10-19
Applicant: 삼성전자주식회사
IPC: H01L27/115 , B82Y10/00
CPC classification number: H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524 , H01L21/28273
Abstract: A flash memory device is provided to avoid a soft program caused by a hot carrier phenomenon by making a junction region of a string select transistor and a ground select transistor have a DDD(double doped drain) structure while maintaining shallow junction regions of memory cell transistors. A semiconductor substrate(100) has an isolation region confining an active region, a string select line and a ground select line crosses the active region. A plurality of wordlines are arranged between the string select line and the ground select line. First impurity regions(113) with a first depth are formed between the plurality of wordlines. Second impurity regions(115,116) with a second depth deeper than the first depth are formed between the string select line and its adjacent wordline and between the ground select line and its adjacent wordline. The second impurity regions can additionally be formed between adjacent string select lines.
Abstract translation: 提供闪存器件以避免由热载流子现象引起的软程序，使得串选择晶体管和接地选择晶体管的结区具有DDD（双掺杂漏极）结构，同时保持存储单元晶体管的浅结区 。 半导体衬底（100）具有限制有源区域，串选择线和接地选择线的隔离区域与有源区域交叉。 多个字线被布置在弦选择线和地选线之间。 在多个字线之间形成具有第一深度的第一杂质区域（113）。 在串选择线及其相邻字线之间以及地线选择线与其相邻字线之间形成第二深度比第一深度深的第二杂质区（115,116）。 另外可以在相邻的串选择线之间形成第二杂质区。
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公开(公告)号：KR1020100011196A
公开(公告)日：2010-02-03
申请号：KR1020080072315
申请日：2008-07-24
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/768
CPC classification number: G11C16/3454 , G11C16/0483 , G11C16/10 , H01L27/11551 , H01L27/11556 , H01L27/2463
Abstract: PURPOSE: A non-volatile semiconductor memory device and a memory system including the same are provided to obtain uniform electric potential by driving a bit line and a source line with the same voltage as the bit line according to same voltage. CONSTITUTION: A source line(120) is arranged in the same direction of a bit line(110). A string(150) is formed between the bit line and a source line vertically. Each source line is arranged in order to be in common with strings connected to the bit line. A source line is driven by the same voltage of the bit line. Each string comprises memory cells which are serially connected between the first selecting transistor and the second selection transistor, the first selection transistors, and the second selection transistors. The source line is formed on the semiconductor substrate(140) by N type material. The source line is formed on the semiconductor substrate by metal.
Abstract translation: 目的：提供一种非易失性半导体存储器件和包括该非易失性半导体存储器件的存储器系统，以通过根据相同的电压驱动与位线相同电压的位线和源极线来获得均匀的电位。 构成：源极线（120）沿位线（110）的相同方向排列。 在位线和源极线之间垂直形成一串（150）。 每个源极线被布置成与连接到位线的串相同。 源极线由位线的相同电压驱动。 每个串包括串联连接在第一选择晶体管和第二选择晶体管之间的存储单元，第一选择晶体管和第二选择晶体管。 源极线通过N型材料形成在半导体衬底（140）上。 源极线通过金属形成在半导体衬底上。
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公开(公告)号：KR1020090108953A
公开(公告)日：2009-10-19
申请号：KR1020080034316
申请日：2008-04-14
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , G11C16/10
Abstract: PURPOSE: A non-volatile memory device and program method thereof are provided to reduce the boosted electric potential difference between each local channel. CONSTITUTION: A nonvolatile memory programming device includes a floating, a boosting and a floated channel`s electric potential. The floating floats the channel of the cell string from which a program is prohibited. The boosting boosts the floated channel to a plurality of the local channel by supplying string selection and the word line voltage line voltage. The floated channel`s electric potential is lower than the reference level.
Abstract translation: 目的：提供一种非易失性存储器件及其编程方法，以减小每个本地通道之间的升压电位差。 构成：非易失性存储器编程设备包括浮动，升压和浮置通道的电位。 浮动浮动程序被禁止的单元格串的通道。 升压通过提供串选择和字线电压线电压将浮动通道提升到多个本地通道。 浮动通道的电位低于参考电平。
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公开(公告)号：KR1020070013892A
公开(公告)日：2007-01-31
申请号：KR1020050068567
申请日：2005-07-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L21/28273 , H01L21/823437 , H01L29/42324 , H01L29/66825
Abstract: A nonvolatile memory device and a manufacturing method thereof are provided to restrain the convergence of an electric field between a first corner of an active region and a second corner of a floating gate by using an insulating pattern. An isolation layer(60) for defining an active region is formed on a semiconductor substrate(50). A tunnel insulating layer(70) is formed on the active region. An insulating pattern(66) is formed at an edge portion of the active region. A floating gate(72f) is formed on the tunnel insulating layer and the insulating pattern. A control gate electrode(76) is formed on the floating gate. The control gate electrode crosses over the active region and the isolation layer. An inter-gate dielectric is interposed between the floating gate and the control gate. The insulating pattern contacts a lower edge portion and a sidewall of the floating gate.
Abstract translation: 提供一种非易失性存储器件及其制造方法，以通过使用绝缘图案来抑制有源区域的第一拐角和浮动栅极的第二拐角之间的电场的会聚。 在半导体衬底（50）上形成用于限定有源区的隔离层（60）。 隧道绝缘层（70）形成在有源区上。 绝缘图案（66）形成在有源区域的边缘部分。 在隧道绝缘层和绝缘图案上形成浮栅（72f）。 在浮动栅极上形成控制栅电极（76）。 控制栅电极跨越有源区和隔离层。 栅极间电介质介于浮栅和控制栅之间。 绝缘图案接触浮动栅极的下边缘部分和侧壁。
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公开(公告)号：KR101525498B1
公开(公告)日：2015-06-03
申请号：KR1020080122600
申请日：2008-12-04
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L27/088 , H01L21/823462 , H01L21/823493
Abstract: 본발명은반도체장치및 그의제조방법에관한것으로서, 더욱구체적으로는제1두께를갖는제1게이트절연막을포함하는제1트랜지스터및 상기제1두께보다얇은제2두께를갖는제2게이트절연막을포함하는제2트랜지스터를포함하는반도체장치에있어서, 상기제1게이트절연막또는상기제2게이트절연막상에형성되는소자중의적어도하나는더미웰(dummy well)을포함하는반도체장치. 및그의제조방법에관한것이다. 본발명의반도체장치의제조방법을이용하면반도체장치를훨씬간단한공정을통해저렴한가격으로제조할수 있는효과가있다.
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Patent Agency Ranking
公开(公告)号：KR101469105B1
公开(公告)日：2014-12-05
申请号：KR1020080072315
申请日：2008-07-24
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/768
CPC classification number: G11C16/3454 , G11C16/0483 , G11C16/10 , H01L27/11551 , H01L27/11556
Abstract: 여기에제공되는불 휘발성반도체메모리장치는비트라인들과; 상기비트라인들에각각대응하며, 각각이대응하는비트라인과동일한방향으로배열된소오스라인들과; 그리고상기비트라인들과상기소오스라인들사이에수직하게각각형성된스트링들을포함하는수직어레이를구비한다.
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公开(公告)号：KR1020090120205A
公开(公告)日：2009-11-24
申请号：KR1020080046129
申请日：2008-05-19
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3454
Abstract: PURPOSE: A flash memory device and an operation method thereof for programming a selection transistor are provided to prevent the leakage according to the apparatus demagnification by programming the selection transistor. CONSTITUTION: A flash memory device(100) includes a memory cell array, a floating gate, a control gate, and a reading/writing circuit. The memory cell array includes a string selection transistor, a ground-selection transistor and a plurality of strings. A plurality of strings includes memory cells which serially connected between selection transistors.
Abstract translation: 目的：提供一种用于对选择晶体管进行编程的闪速存储器件及其操作方法，以通过对选择晶体管进行编程来防止根据器件缩小的泄漏。 构成：闪存器件（100）包括存储单元阵列，浮动栅极，控制栅极和读/写电路。 存储单元阵列包括串选择晶体管，接地选择晶体管和多个串。 多个串包括串联连接在选择晶体管之间的存储单元。
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公开(公告)号：KR100855579B1
公开(公告)日：2008-09-03
申请号：KR1020060097321
申请日：2006-10-02
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/115 , H01L27/11521
Abstract: 반도체 메모리 장치 및 그 형성 방법이 제공된다. 상기 반도체 메모리 장치는 반도체 기판 상에 위치하는 선택 트랜지스터들과 셀 트랜지스터들, 상기 선택 트랜지스터들과 상기 셀 트랜지스터들을 덮는 절연막, 상기 절연막 내에 배치되고 상기 선택 트랜지스터들 각각에 전기적으로 연결되는 비트라인들을 포함하며, 상기 비트라인들은 적어도 둘 이상의 높이에 배치된다.
낸드형 플래시 메모리, 비트라인, 스트링 선택 트랜지스터-
公开(公告)号：KR101407361B1
公开(公告)日：2014-06-13
申请号：KR1020080034316
申请日：2008-04-14
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , G11C16/10
Abstract: 본 발명에 따른 로컬 셀프-부스팅 방식으로 프로그램 금지 동작을 수행하는 플래시 메모리 장치의 프로그램 방법은, (a) 프로그램 금지된 셀 스트링의 채널을 플로팅(Floating)하는 단계; 및 (b) 워드 라인 전압 및 스트링 선택 라인 전압을 공급하여 상기 플로팅된 채널을 복수의 로컬 채널들로 부스팅(Boosting)하는 단계를 포함하되, 상기 복수의 로컬 채널들 간의 전위차가 소정 레벨보다 낮게 유지되도록 상기 플로팅된 채널 전위 또는 상기 워드 라인 전압이 제공된다.
상술한 프로그램 방법에 따라 부스팅되는 로컬 채널들 간의 전위차로부터 유발되는 핫 케리어 효과에 의한 프로그램 디스터브를 차단할 수 있다.-
公开(公告)号：KR1020100064160A
公开(公告)日：2010-06-14
申请号：KR1020080122600
申请日：2008-12-04
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L27/088 , H01L21/823462 , H01L21/823493
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce a manufacturing time and costs by implementing an NMOS and a PMOS with regard to two kinds of gate insulation layers using a photolithography process twice. CONSTITUTION: A first transistor(160a) includes a first gate insulation layer with a first thickness. A second transistor(160b) includes a second gate insulation layer with a second thickness thinner than a first thickness. At least one of elements formed on a first gate insulation layer or second gate insulation layer includes a dummy well(130). The lower surface of the first gate insulation layer and the lower surface of the second gate insulation layer are formed on the substantially same plane.
Abstract translation: 目的：提供一种半导体器件及其制造方法，以通过使用光刻工艺两次对两种栅极绝缘层实施NMOS和PMOS来减少制造时间和成本。 构成：第一晶体管（160a）包括具有第一厚度的第一栅绝缘层。 第二晶体管（160b）包括具有比第一厚度薄的第二厚度的第二栅绝缘层。 形成在第一栅极绝缘层或第二栅极绝缘层上的至少一个元件包括虚拟阱（130）。 第一栅极绝缘层的下表面和第二栅极绝缘层的下表面形成在基本相同的平面上。
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