公开(公告)号：KR1020140070515A

公开(公告)日：2014-06-10

申请号：KR1020140061011

申请日：2014-05-21

Applicant: 삼성전자주식회사

Inventor： 곽기원 ,  주창남 ,  강춘운 ,  고민우 ,  정민우 ,  윤정수

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0877 ,  H04L9/3234 ,  H04L2209/603

Abstract: The present invention relates to a method and an apparatus for providing an encryption key based on a DRM type of a host apparatus and, more specifically, to a method and an apparatus for guaranteeing the compatibility of the host apparatus by providing the encryption key according to the DRM type of the host apparatus. The method for providing the encryption key based on the DRM type of the host apparatus according to an embodiment of the present invention comprises a step of receiving available DRM type information from the host apparatus and determining the received available DRM type; a step of generating a content key container based on a modulation key of content used by the host apparatus; a step of requesting the generation of a key object by transmitting the determined DRM type, the generated content key container, the use right of the content, and meta data to a DRM providing server; and a step of transmitting the generated key object to the host apparatus according to the request.

Abstract translation: 本发明涉及一种用于提供基于DRM类型的主机设备的加密密钥的方法和装置，更具体地，涉及一种用于通过提供根据本发明的加密密钥来保证主机设备的兼容性的方法和装置 主机设备的DRM类型。 根据本发明实施例的用于提供基于主机设备的DRM类型的加密密钥的方法包括从主机设备接收可用DRM类型信息并确定接收到的可用DRM类型的步骤; 基于所述主机装置使用的内容的调制密钥生成内容密钥容器的步骤; 通过将所确定的DRM类型，所生成的内容密钥容器，内容的使用权和元数据发送到DRM提供服务器来请求生成密钥对象的步骤; 以及根据请求将生成的密钥对象发送到主机设备的步骤。

公开(公告)号：KR1020130114484A

公开(公告)日：2013-10-18

申请号：KR1020120036902

申请日：2012-04-09

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  박인선 ,  이종명 ,  홍종원 ,  김회승 ,  윤정수

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to increase an aspect ratio by forming self-aligned top conductive patterns. CONSTITUTION: Switching elements are formed on a substrate. A bottom structure is formed on the substrate. A bottom conductive layer is formed on the bottom structure (S10). Sacrificial mask patterns are formed on the bottom conductive layer (S15). Bottom conductive patterns and top conductive patterns are formed in opening parts (S40). [Reference numerals] (S10) Bottom conductive film is formed; (S15) Sacrificial mask patterns are formed; (S20) Bottom conductive patterns are formed by etching the bottom conductive film; (S25) Inter-layer insulation film is formed between layers; (S30) Sacrificial mask patterns are exposed by flattening the inter-layer insulation film; (S35) Opening parts are formed by removing the exposed sacrificial mask patterns; (S40) Top conductive patterns are formed in the opening parts; (S5) Bottom insulation film is formed on a substrate

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过形成自对准的顶部导电图案来增加纵横比。 构成：开关元件形成在基板上。 在基板上形成底部结构。 在底部结构上形成底部导电层（S10）。 牺牲掩模图案形成在底部导电层上（S15）。 底部导电图案和顶部导电图案形成在开口部分中（S40）。 （附图标记）（S10）形成底部导电膜; （S15）形成牺牲掩模图案; （S20）通过蚀刻底部导电膜形成底部导电图案; （S25）层之间形成层间绝缘膜; （S30）通过使层间绝缘膜变平而露出牺牲掩模图案; （S35）通过去除曝光的牺牲掩模图案形成开口部分; （S40）在开口部形成有顶部导电图案， （S5）在基板上形成底部绝缘膜

公开(公告)号：KR1020130063564A

公开(公告)日：2013-06-17

申请号：KR1020110129966

申请日：2011-12-07

Applicant: 삼성전자주식회사

Inventor： 윤정수 ,  홍종원 ,  박인선 ,  이종명 ,  최승욱

IPC: H01L21/31

CPC classification number: H01L29/0607 ,  H01L23/3192 ,  H01L23/562 ,  H01L27/108 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor device and a method for fabricating the same are provided to effectively reduce leakage current by using a first passivation layer for preventing the outgassing of hydrogen. CONSTITUTION: Lines(9,34,48) are arranged on a substrate(1). An interlayer insulating layer(7,11,30) covers the lines. A first passivation layer(50) is arranged on the interlayer insulating layer. A second passivation layer(52) is arranged on the first passivation layer. The density of the second passivation layer is lower than that of the first passivation layer. A third passivation layer(54) is arranged on the second passivation layer.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过使用用于防止氢气除气的第一钝化层来有效地减少泄漏电流。 线条（9,34,48）布置在基片（1）上。 层间绝缘层（7,11,30）覆盖线。 第一钝化层（50）布置在层间绝缘层上。 第二钝化层（52）布置在第一钝化层上。 第二钝化层的密度低于第一钝化层的密度。 第三钝化层（54）布置在第二钝化层上。