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    반도체 장치의 제조 방법 및 이에 의해 제조된 반도체 장치
    2.
    发明公开
    반도체 장치의 제조 방법 및 이에 의해 제조된 반도체 장치 审中-实审
    形成半导体器件的方法和由该方法形成的器件

    公开(公告)号：KR1020130063578A

    公开(公告)日：2013-06-17

    申请号：KR1020110129985

    申请日：2011-12-07

    Applicant: 삼성전자주식회사

    Inventor： 홍종원 ,  박인선 ,  김회승 ,  백종민

    IPC: H01L21/28

    CPC classification number: H01L21/76877 ,  C25D3/38 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/522 ,  H01L27/04 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PURPOSE: A method for forming a semiconductor device and the semiconductor device formed by the method are provided to form a uniform plating layer having no void in a cell pattern region. CONSTITUTION: An interlayer insulating layer is formed on the front surface of a substrate including a cell array region and a peripheral circuit region(S10). The interlayer insulating layer is etched to form cell recess regions and at least one dummy recess region in the cell array region(S20). A seed layer is formed on the interlayer insulating layer(S30). An electroplating process is performed to form a plating layer for filling the cell recess regions and the dummy recess region(S40). [Reference numerals] (S10) Step of forming an interlayer insulating layer on a substrate; (S20) Step of forming a cell recess region and a dummy recess region on the interlayer insulating layer; (S30) Step of forming a seed layer on the interlayer insulating layer; (S40) Step of forming a plating layer in the cell recess region and the dummy recess region by processing an electroplating process

    Abstract translation: 目的：提供一种形成半导体器件的方法和通过该方法形成的半导体器件，以在电池图案区域中形成不具有空隙的均匀镀层。 构成：在包括电池阵列区域和外围电路区域的衬底的前表面上形成层间绝缘层（S10）。 蚀刻层间绝缘层以形成电池阵列区域中的电池凹部区域和至少一个虚设凹部区域（S20）。 在层间绝缘层上形成种子层（S30）。 进行电镀工艺以形成用于填充电池凹部区域和虚设凹部区域的电镀层（S40）。 （S10）在衬底上形成层间绝缘层的步骤; （S20）在层间绝缘层上形成单元凹部区域和虚设凹部区域的工序; （S30）在层间绝缘层上形成种子层的工序; （S40）通过处理电镀工序在电池凹部区域和虚设凹部区域形成镀层的工序

    반도체 장치 및 그 제조 방법
    3.
    发明公开
    반도체 장치 및 그 제조 방법 审中-实审
    半导体器件及其制造方法

    公开(公告)号：KR1020130060432A

    公开(公告)日：2013-06-10

    申请号：KR1020110126479

    申请日：2011-11-30

    Applicant: 삼성전자주식회사

    Inventor： 홍종원 ,  김회승 ,  남경희 ,  박인선 ,  이종명

    IPC: H01L21/28 ,  H01L21/8229 ,  H01L27/105

    CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PURPOSE: A semiconductor device and a method for manufacturing the same are provided to improve an electrical characteristic by forming a copper line structure which has a metal pattern and no void. CONSTITUTION: A substrate(100) includes a cell region and a peripheral circuit region. A trench(120) is formed in the upper part of an interlayer insulating layer(110). A line structure(180) fills a trench passing through a part of the interlayer insulating layer. The line structure includes a barrier layer pattern(135), a metal pattern(175), and a wetting promotion layer pattern(165). The metal pattern has no void. The wetting promotion film pattern is formed in the central part of the trench.

    Abstract translation: 目的：提供半导体器件及其制造方法，通过形成具有金属图案且无空隙的铜线结构来改善电特性。 构成：衬底（100）包括单元区域和外围电路区域。 沟槽（120）形成在层间绝缘层（110）的上部。 线结构（180）填充通过层间绝缘层的一部分的沟槽。 线结构包括阻挡层图案（135），金属图案（175）和润湿促进层图案（165）。 金属图案没有空隙。 润湿促进膜图案形成在沟槽的中心部分。

    도전 패턴 구조물 및 이의 형성 방법
    4.
    发明公开
    도전 패턴 구조물 및 이의 형성 방법 有权
    电气图案结构及其制造方法

    公开(公告)号：KR1020120088181A

    公开(公告)日：2012-08-08

    申请号：KR1020110009342

    申请日：2011-01-31

    Applicant: 삼성전자주식회사

    Inventor： 김회승 ,  박인선 ,  최길현 ,  박지순 ,  이종명 ,  홍종원

    IPC: H01L21/033 ,  H01L21/288 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532 ,  H01L27/02 ,  H01L21/768 ,  H01L27/115

    CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PURPOSE: A conductive pattern structure and a method of forming thereof are provided to prevent operation errors of a semiconductor element due to the defect of the copper wiring by forming the copper wiring in uniform thickness on entire area of a substrate. CONSTITUTION: A substrate includes a first area and a second area. A first interlayer insulating film is formed on the substrate. First and second conductive patterns(26a,26b) and first and second dummy conductive patterns(26c,26d) are formed on the first interlayer insulating film of the first area. First and second dummy conductive patterns are formed on the first interlayer insulating film of the second area. A second interlayer insulating film is filled between the second conductive pattern and the first and second dummy conductive patterns.

    Abstract translation: 目的：提供导电图案结构及其形成方法，以通过在基板的整个区域上形成均匀厚度的铜布线来防止由于铜布线的缺陷导致的半导体元件的操作误差。 构成：衬底包括第一区域和第二区域。 在基板上形成第一层间绝缘膜。 第一和第二导电图案（26a，26b）和第一和第二虚设导电图案（26c，26d）形成在第一区域的第一层间绝缘膜上。 第一和第二虚设导电图案形成在第二区域的第一层间绝缘膜上。 第二层间绝缘膜填充在第二导电图案和第一和第二虚设导电图案之间。

    도전 패턴 구조물 및 이의 형성 방법
    8.
    发明授权
    도전 패턴 구조물 및 이의 형성 방법 有权
    导电图案结构及其形成方法

    公开(公告)号：KR101762657B1

    公开(公告)日：2017-07-31

    申请号：KR1020110009342

    申请日：2011-01-31

    Applicant: 삼성전자주식회사

    Inventor： 김회승 ,  박인선 ,  최길현 ,  박지순 ,  이종명 ,  홍종원

    IPC: H01L21/033 ,  H01L21/288 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532 ,  H01L27/02 ,  H01L21/768 ,  H01L27/115

    CPC classification number: H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: 도전패턴구조물및 이의형성방법에서, 도전패턴구조물은, 제1 및제2 영역이구분된기판상에층간절연막이구비된다. 상기제1 영역의층간절연막내에는셀 블록양 단부까지제1 방향으로연장되는제1 도전패턴들이구비된다. 상기제1 도전패턴과인접하는제2 영역의층간절연막내에는상기셀 블록의중간에서끊어지는형상을갖고제1 방향으로연장되는제2 도전패턴이구비된다. 상기제2 도전패턴과인접하게배치되고, 셀블록의양 단부까지제1 방향으로연장되는제1 더미도전패턴이구비된다. 상기제2 도전패턴양측으로셀 블록의양 단부까지제1 방향으로연장되는도전패턴들이구비됨으로써, 상기제2 도전패턴은기판전 영역에서균일한두께를가질수 있다.

    Abstract translation: 在导电图案结构及其形成方法中，导电图案结构在其中第一区域和第二区域分离的基板上设置有层间绝缘膜。 在第一区域的层间绝缘膜中，设置沿着第一方向延伸至单元块的两端的第一导电图案。 并且在与第一导电图案相邻的第二区域的层间绝缘膜中设置具有在单元块的中间切割并沿第一方向延伸的形状的第二导电图案。 以及第一虚设导电图案，所述第一虚设导电图案与所述第二导电图案相邻设置并且沿着第一方向延伸到所述单元块的两端。 通过在第一方向上在第二导电图案的两侧上设置在单元块的两个方向上延伸的导电图案，第二导电图案可以在整个衬底中具有均匀的厚度。

    반도체 소자의 제조방법
    10.
    发明公开
    반도체 소자의 제조방법 无效
    一种制造半导体器件的方法

    公开(公告)号：KR1020130114484A

    公开(公告)日：2013-10-18

    申请号：KR1020120036902

    申请日：2012-04-09

    Applicant: 삼성전자주식회사

    Inventor： 백종민 ,  박인선 ,  이종명 ,  홍종원 ,  김회승 ,  윤정수

    IPC: H01L21/3205 ,  H01L21/28

    CPC classification number: H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

    Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to increase an aspect ratio by forming self-aligned top conductive patterns. CONSTITUTION: Switching elements are formed on a substrate. A bottom structure is formed on the substrate. A bottom conductive layer is formed on the bottom structure (S10). Sacrificial mask patterns are formed on the bottom conductive layer (S15). Bottom conductive patterns and top conductive patterns are formed in opening parts (S40). [Reference numerals] (S10) Bottom conductive film is formed; (S15) Sacrificial mask patterns are formed; (S20) Bottom conductive patterns are formed by etching the bottom conductive film; (S25) Inter-layer insulation film is formed between layers; (S30) Sacrificial mask patterns are exposed by flattening the inter-layer insulation film; (S35) Opening parts are formed by removing the exposed sacrificial mask patterns; (S40) Top conductive patterns are formed in the opening parts; (S5) Bottom insulation film is formed on a substrate

    Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过形成自对准的顶部导电图案来增加纵横比。 构成：开关元件形成在基板上。 在基板上形成底部结构。 在底部结构上形成底部导电层（S10）。 牺牲掩模图案形成在底部导电层上（S15）。 底部导电图案和顶部导电图案形成在开口部分中（S40）。 （附图标记）（S10）形成底部导电膜; （S15）形成牺牲掩模图案; （S20）通过蚀刻底部导电膜形成底部导电图案; （S25）层之间形成层间绝缘膜; （S30）通过使层间绝缘膜变平而露出牺牲掩模图案; （S35）通过去除曝光的牺牲掩模图案形成开口部分; （S40）在开口部形成有顶部导电图案， （S5）在基板上形成底部绝缘膜

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