Abstract:
PURPOSE: A cache memory system for tile based rendering and a cache method thereof are provided to use delay replacement information of a cache line, thereby selecting a removed cache line. CONSTITUTION: A first linkage cache unit(210) searches a cache line corresponding to an accessed address among first cache lines. A second linkage cache unit stores second cache lines and searches a cache line corresponding to an accessed address among the second cache lines. The first linkage cache unit includes delay replacement information of the first cache lines. [Reference numerals] (AA) Memory address; (BB) Tag field; (CC) Set field; (DD) Word field; (E1,G1) Way 0; (E2,G2) Way 1; (E3,G3) Way k-1; (E4,E8,E12) Delay; (E5,E9,E13) Replacement; (E6,E10,E14) Information; (E7,E11,E15,L1,L2,L3) Tag; (F1) Set 0; (F2) Set 1; (F3) Set 2; (G4,G7,G10) Word 0; (G5,G8,G11) Word 1; (G6,G9,G12) Word 2; (HH,NN) Hit; (II) Comparison; (JJ) Primary miss; (KK) Data from a next lower memory layer; (M1,M2,M3) Data of a first cache line; (OO) Secondary miss; (PP) Address to the next lower memory layer;
Abstract:
The present invention relates to a non-blocking texture cache memory system for a texture mapping pipeline and a method for operating a non-blocking texture cache memory. The texture cache memory includes a retry buffer which temporarily stores result data by a heat pipeline or a miss pipeline, a retry buffer lookup unit which looks up the retry buffer in response to a texture request transmitted from a processor, a checking unit which checks whether the result data corresponding to the texture request is stored in the retry buffer from the lookup result, and an output control unit which outputs the stored result data to the processor if the checking result shows that the result data corresponding to the texture request is stored.
Abstract:
A method and apparatus for providing shared caches are provided. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, tag bits and set index bits among bits of a memory address overlap each other as much as at least one bit. [Reference numerals] (110) First cache; (120) Second cache; (130) First comparison unit; (140) Second comparison unit; (150) Determination unit; (410) Third memory address; (412) Tag; (414) Set index; (416) Word; (AA) Hit or miss; (BB) Hit; (CC) Miss; (DD) Hit or miss; (EE,FF) Tag data; (GG) Address to an external memory; (HH) Data from the external memory
Abstract:
본 발명은 3차원 그래픽 가속기를 위한 부동소수점 누승기장치 및 그 처리방법에 관한 것으로, 지수연산 처리장치에 있어서, 부동소수점을 고정소수점으로 변환된 데이터로 출력하는 제1 입력부, 부동소수점을 데이터 그대로 입력받는 제2 입력부, 상기 제2 입력부의 출력신호값에 따라 생성되는 값을 가지는 제1 테이블부, 상기 제1 입력부의 출력신호값과 상기 제1 테이블부의 데이터값을 연산하는 제1 연산부, 상기 제1 연산부의 출력신호값에 따라 생성되는 값을 가지는 제2 테이블부, 상기 제1 연산부의 출력신호값과 상기 제2 테이블부의 데이터값을 연결하는 제2 연산부로 구성되고, 상기 제2 연산부는 최종 결과값(P)을 부동소수점 형식의 지수부분과 분수부분을 연결하는 것을 특징으로 한다. 상기와 같은 3차원 그래픽 가속기를 위한 부동소수점 누승기장치 및 그 처리방법을 이용하는 것에 의해, 변환부는 부동소수점에서 고정소수점으로의 변환장치가 필요하지 않으므로 부동소수점 누승기장치의 구성을 간단하게 할 수 있다. 누승기, 부동소수점, 고정소수점, 지수, 로그