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公开(公告)号：KR101477053B1
公开(公告)日：2014-12-31
申请号：KR1020140019135
申请日：2014-02-19
Applicant: 연세대학교 산학협력단
CPC classification number: G04F10/005 , H03K5/135 , H03L7/085 , H03L2207/50
Abstract: The present invention relates to a time-digital converter and a phase-locked loop circuit using the same.The time-digital converter according to an embodiment of the present invention includes: a first stage of delaying a start signal by a first delay time to compare a stop signal with the delayed start signal or delaying the stop signal by a second delay time to compare the delayed stop signal with the delayed start signal; a second stage of delaying the start signal output from the first stage by a third delay time to compare the stop signal output from the first stage with the third delayed start signal or delaying the stop signal output from the first stage by a forth delay time to compare the fourth delayed stop signal with the third delayed start signal; and a controller which circularly inputs the start signal and the stop signal output from the second stage a preset number of times, and changes the first to fourth delay times every circle.
Abstract translation: 本发明涉及一种时数数字转换器和使用该数字转换器的锁相环电路。根据本发明实施例的时数转换器包括：将起始信号延迟第一延迟时间的第一级， 将停止信号与延迟的起始信号进行比较，或将停止信号延迟第二延迟时间，以将延迟的停止信号与延迟的起始信号进行比较; 将从第一级输出的起始信号延迟第三延迟时间的第二级，以将从第一级输出的停止信号与第三延迟开始信号进行比较，或将从第一级输出的停止信号延迟第四延迟时间， 将第四延迟停止信号与第三延迟启动信号进行比较; 以及将从第二级输出的开始信号和停止信号循环输入预定次数的控制器，并且每循环改变第一至第四延迟时间。
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公开(公告)号：KR102022547B1
公开(公告)日：2019-09-18
申请号：KR1020150094562
申请日：2015-07-02
Applicant: 에스케이하이닉스 주식회사 , 연세대학교 산학협력단
IPC: G01R19/165 , G01R31/00 , G01R31/26
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公开(公告)号：KR1020170004340A
公开(公告)日：2017-01-11
申请号：KR1020150094562
申请日：2015-07-02
Applicant: 에스케이하이닉스 주식회사 , 연세대학교 산학협력단
IPC: G01R19/165 , G01R31/00 , G01R31/26
CPC classification number: G01R31/2621 , G01R31/06
Abstract: 본기술에의한문턱전압측정장치는모스트랜지스터, 모스트랜지스터의드레인전압을고정하는드레인전압고정부; 모스트랜지스터에드레인-소스전류를인가하는정전류공급부를포함한다.
Abstract translation: 阈值电压测量装置可以包括金属氧化物半导体（MOS）晶体管，漏极电压钳位电路，被配置为控制MOS晶体管的漏极电压，其中漏极电压具有基本上恒定的电平，以及恒定电流供应电路配置 以使漏源电流流过MOS晶体管，其中漏 - 源电流具有基本恒定的量级。
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Patent Agency Ranking
公开(公告)号：KR101383223B1
公开(公告)日：2014-04-14
申请号：KR1020120091899
申请日：2012-08-22
Applicant: 연세대학교 산학협력단
Abstract: 본 발명은 지연 회로 및 지연 제어 방법에 관한 것으로, 병렬 연결된 전송게이트들; 선형적 지연스텝들에 대응하는 상기 전송게이트들의 턴온(turn-on) 조합에 관한 정보를 나타내는 룩업테이블을 생성하는 룩업테이블 생성부; 및 생성된 상기 룩업테이블의 상기 턴온 조합에 관한 정보를 이용하여, 상기 전송게이트들을 제어하기 위한 제어코드를 생성하는 제어코드 생성부를 포함하는 지연 회로를 제공한다.
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公开(公告)号：KR101342093B1
公开(公告)日：2013-12-18
申请号：KR1020120077897
申请日：2012-07-17
Applicant: 연세대학교 산학협력단
CPC classification number: H03K5/133 , G11C7/1093 , G11C7/222 , H03K2005/00058 , H03L7/0818
Abstract: The present invention relates to a delay circuit which includes delay cells connected in series. One or more delay cells among the delay cells in the delay circuit includes: a first try state inverter which selectively reverses a forward direction input signal from a first delay cell depending on a control signal and then outputs to the forward direction input terminal of a second delay cell; a second try state inverter which selectively reverses the forward direction input signal depending on the control signal and outputs to the reverse direction input terminal of the first delay cell; a third try state inverter which selectively reverses the reverse direction output signal from the second delay cell depending on the control signal and outputs to the reverse direction input terminal of the first delay cell; and a floating prevention circuit for preventing a floating of the forward direction input terminal of the second delay cell. [Reference numerals] (110) Control signal generating unit
Abstract translation: 延迟电路技术领域本发明涉及一种包括延迟单元串联连接的延迟电路。 延迟电路中的延迟单元中的一个或多个延迟单元包括：第一测试状态反相器，其根据控制信号选择性地反转来自第一延迟单元的正向输入信号，然后输出到第二延迟单元的正向输入端 延迟细胞 第二尝试状态反相器，其根据控制信号选择性地反转正向输入信号，并输出到第一延迟单元的反向输入端; 第三尝试状态反相器，其根据控制信号选择性地反转来自第二延迟单元的反向输出信号，并输出到第一延迟单元的反向输入端; 以及用于防止第二延迟单元的正向输入端的浮置的浮动防止电路。 （附图标记）（110）控制信号生成单元
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公开(公告)号：KR101943717B1
公开(公告)日：2019-01-29
申请号：KR1020160179026
申请日：2016-12-26
Applicant: 연세대학교 산학협력단
IPC: G01J1/44
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公开(公告)号：KR1020150117761A
公开(公告)日：2015-10-21
申请号：KR1020140043045
申请日：2014-04-10
Applicant: 연세대학교 산학협력단
CPC classification number: H03L7/0895 , H02M3/07 , H03L7/08
Abstract: 본발명은전하펌프및 위상동기루프에관한것으로, 본발명의실시예에따른전하펌프는, 제1 게이트에풀업(pull-up) 신호가인가되는제1 스위칭트랜지스터; 제2 게이트에풀다운(pull-down) 신호가인가되는제2 스위칭트랜지스터; 제1 전류미러를통해제1 스위칭트랜지스터에풀업전류를형성하는제1 전류소스트랜지스터; 및제2 전류미러를통해제2 스위칭트랜지스터에풀다운전류를형성하는제2 전류소스트랜지스터를포함하고, 제1 전류소스트랜지스터및 제2 전류소스트랜지스터의바디(body)에, 제1 스위칭트랜지스터와제2 스위칭트랜지스터의드레인또는소스사이에형성되는제어전압이인가된다.
Abstract translation: 本发明涉及电荷泵和锁相环。 根据本发明实施例的电荷泵包括：具有施加上拉信号的第一栅极的第一开关晶体管; 具有施加了下拉信号的第二栅极的第二开关晶体管; 第一电流源晶体管，其经由第一电流镜在所述第一开关晶体管处形成上拉电流; 以及第二电流源晶体管，其经由第二电流镜在所述第二开关晶体管处形成下拉电流，其中形成在所述第一开关晶体管的漏极或源极与所述第二开关晶体管之间的控制电压施加到所述主体 的第一电流源晶体管和第二电流源晶体管。
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公开(公告)号：KR101262322B1
公开(公告)日：2013-05-09
申请号：KR1020110141298
申请日：2011-12-23
Applicant: 연세대학교 산학협력단
CPC classification number: H03L7/00 , H03L7/0816 , H03L7/0818 , H03L7/087
Abstract: PURPOSE: A delay locked loop is provided to reduce the maximum static phase offset. CONSTITUTION: A delay locked loop includes a delay signal generation unit(100), a phase synthesis unit(200) and a phase detection unit(300). The delay signal generation unit delays a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal based on a delay control signal. The phase synthesis unit generates a third signal having a third phase using the first delay signal and the second delay signal. The phase detection unit generates a control code by comparing the first, the second, and the third delay signals with the reference signal. [Reference numerals] (110) First fine delay line; (120) Second fine delay line; (200) Phase synthesis unit; (310) First detection unit; (320) Second detection unit; (330) Third detection unit; (400) Phase control signal generation unit; (500) Delay control signal generation unit; (600) First MUX; (700) Second MUX; (800) Coarse delay line
Abstract translation: 目的：提供延迟锁定环以减少最大静态相位偏移。 构成：延迟锁定环包括延迟信号生成单元（100），相位合成单元（200）和相位检测单元（300）。 延迟信号生成单元通过延迟基于延迟控制信号的参考信号来延迟具有第一相位的第一延迟信号和具有第二相位的第二延迟信号。 相位合成单元使用第一延迟信号和第二延迟信号产生具有第三相位的第三信号。 相位检测单元通过将第一，第二和第三延迟信号与参考信号进行比较来产生控制码。 （附图标记）（110）第一细延迟线; （120）第二细延时线; （200）相合成单元; （310）第一检测单元; （320）第二检测单元; （330）第三检测单元; （400）相位控制信号发生单元; （500）延时控制信号发生单元; （600）第一MUX; （700）第二MUX; （800）粗延时线
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