公开(公告)号：KR100324253B1

公开(公告)日：2002-02-25

申请号：KR1019990056733

申请日：1999-12-10

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: 본발명은시스템의전력을낮추기위하여정적명령어추출과인스트럭션디코드룩어사이드버퍼(I-DLB)를이용하는마이크로프로세서를위한저전력인스트럭션디코딩방법에관한것으로써, 마이크로프로세서설계단계의시뮬레이션에서응용프로그램수행시자주사용되는소수의명령어들의비트(bit)중, 인스트럭션디코더의로직천이를발생시켜전력소모를유발하는비트들로구성된정적명령어집합(SES : Statically Extracted Set)을추출하는제1 과정; 메모리에서읽어온명령어가상기제1 과정에서추출된 SES와같은지를비교하는제2 과정; 상기제2 과정에서명령어와 SES가같다고판단되면인스트럭션디코더회로(I-DLB : Instruction Decode Lookaside Buffer)로연결되는신호를홀드(Hold)하여인스트럭션디코더의로직천이를막고, ROM(Read Only Memory) 형태로되어있는 I-DLB에저장되어있는콘트롤신호를발생하여디코더로직의천이가필요없는신호가명령어로부터추출되도록하는제3 과정; 및상기제2 과정에서명령어와 SES가같지않다고판단되면 I-DLB를디스에이블(disable)시키고, 인스트럭션디코더회로로연결되는신호를메모리에서읽어온명령어와같은값으로하여기존의인스트럭션디코딩과정을수행하도록하는제4 과정;을포함하여이루어지는것을특징으로한다.

公开(公告)号：KR1020010089969A

公开(公告)日：2001-10-17

申请号：KR1020000015405

申请日：2000-03-27

Applicant: 한국과학기술원

Inventor： 우람찬 ,  윤치원 ,  유회준

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: PURPOSE: A memory addressing method is provided, which can increase a memory access speed by varying only memory addressing sequence according to a read and a write operation of a memory without changing a system structure, and also can increase an efficiency of the memory operation. CONSTITUTION: In an SDRAM(Synchronous DRAM) supporting an RAC(Row After Column) addressing method, if a column #1 address signal is inputted, a column path selected by the above column #1 signal is activated and receives data from the external. Then, if a row #1 address signal is inputted, a row path selected by the above row #1 address signal is activated. Then, data is transferred to the row path from the column path, and the row path can operate independently using data transferred without the column path. Therefore, the column path can perform another operation by receiving a new column address.

Abstract translation: 目的：提供存储器寻址方法，其可以通过根据存储器的读取和写入操作改变存储器寻址序列而不改变系统结构来增加存储器访问速度，并且还可以提高存储器操作的效率。 构成：在支持RAC（行后列）寻址方法的SDRAM（同步DRAM）中，如果输入列＃1地址信号，则由上述列＃1信号选择的列路径被激活并从外部接收数据。 然后，如果输入行＃1地址信号，则由上述行＃1地址信号选择的行路径被激活。 然后，数据从列路径传输到行路径，并且行路径可以使用没有列路径传输的数据独立运行。 因此，列路径可以通过接收新的列地址来执行另一操作。

公开(公告)号：KR100505134B1

公开(公告)日：2005-08-02

申请号：KR1020030037038

申请日：2003-06-10

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06F7/52

CPC classification number: G06T15/005 ,  G06T15/04 ,  G06T2200/28

Abstract: 본 발명은 3차원 컴퓨터 그래픽 시스템의 제산유니트에 관한 것으로서, 3차원 컴퓨터 그래픽 시스템에서 텍스쳐 매핑에 사용되는 원근제법의 제산과정시 호모지니어스 텍스쳐주소인 w에서의 선행 제로의 수만큼을 u, v의 최상위 비트에서 제거하여 적은 크기로 근사적으로 나눗셈을 수행함으로써 면적과 전력을 더욱 줄일 수 있으며, 저전력으로 동작하는 휴대용 기기에서 실시간 텍스쳐 매핑의 성능을 증가시켜 3차원 컴퓨터 그래픽을 보다 현실감 있게 구현할 수 있는 이점이 있다.

公开(公告)号：KR1020040102251A

公开(公告)日：2004-12-04

申请号：KR1020030033574

申请日：2003-05-27

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F13/00

Abstract: PURPOSE: An accelerator for processing multimedia using a coprocessor on a portable system is provided to efficiently process a multimedia data stream with a small power by using a stream buffer including a system interface unit for enabling the coprocessor equipped with a program memory to directly invoke a main processor and being used as an operation register. CONSTITUTION: A coprocessor interface unit(201) connects the main processor(100) and the coprocessor(200). An internal program memory(207) stores the program. A state control unit(208) makes the coprocessor execute instructions of the main processor and requests the needed operation to the main processor. The stream buffer(203) has the system bus interface(202) for directly connecting to a system bus for the multimedia data stream, and reads/stores data on the next stream when the coprocessor performs a stream processing program. A register mapping unit(204) performs mapping in order to make the coprocessor use contents of the stream buffer as an operation register. An SIMD(Single Instruction Multiple Data) data path(206) performs an SIMD operation in order to make the coprocessor process multiple data at one instruction.

Abstract translation: 目的：提供一种用于在便携式系统上使用协处理器处理多媒体的加速器，以通过使用包括系统接口单元的流缓冲器来有效地处理具有小功率的多媒体数据流，以使能配备有程序存储器的协处理器直接调用 主处理器并用作操作寄存器。 构成：协处理器接口单元（201）连接主处理器（100）和协处理器（200）。 内部程序存储器（207）存储程序。 状态控制单元（208）使协处理器执行主处理器的指令并向主处理器请求所需的操作。 流缓冲器（203）具有用于直接连接到用于多媒体数据流的系统总线的系统总线接口（202），并且当协处理器执行流处理程序时，将数据读取/存储在下一个流上。 寄存器映射单元（204）执行映射以使协处理器使用流缓冲器的内容作为操作寄存器。 SIMD（单指令多数据）数据路径（206）执行SIMD操作，以使协处理器在一个指令处理多个数据。

公开(公告)号：KR100448071B1

公开(公告)日：2004-09-10

申请号：KR1020020013838

申请日：2002-03-14

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F13/38

Abstract: PURPOSE: A device for controlling a buffer memory of a computer system is provided to implement a buffer system of a low-power effectively and use an internal memory as a scratch pad memory by partially activating a bank of an internal buffer memory according to a flow of the current data and the number of entry numbers of a queue and applying an adaptability in a queue system for connecting two components which create and consume data. CONSTITUTION: An output latch(40) is operated as a virtual queue when data stored in a buffer memory(20) are transmitted to a consumption component(30) or the buffer memory(20) is used as a scratch pad memory. A buffer controller(50) controls data of the buffer memory(20), and delays an operation of a processor(10) or the component(30) when an overflow or underflow of the buffer memory(20) is generated. The buffer controller(50) decides an active point(Act_point) according to the number of internal entry numbers of the buffer memory(20) and the number of necessary bank numbers. The buffer controller(50) separates an output latch(40) for using the buffer memory(20) as the scratch pad memory. A bank controller(60) activates a bank of the buffer memory(20) as a circular form by the active point(Act_point) of the buffer controller(50).

Abstract translation: 目的：提供一种用于控制计算机系统的缓冲存储器的设备，以有效地实现低功率的缓冲系统，并且通过根据流程部分地激活内部缓冲存储器的存储体而将内部存储器用作高速暂存存储器 当前数据的数量和队列的条目数量，并在队列系统中应用适应性以连接创建和消费数据的两个组件。 构成：当存储在缓冲存储器（20）中的数据被传输到消耗部件（30）或缓冲存储器（20）被用作暂存存储器时，输出锁存器（40）作为虚拟队列操作。 缓冲器控制器（50）控制缓冲存储器（20）的数据，并且当产生缓冲存储器（20）的上溢或下溢时延迟处理器（10）或组件（30）的操作。 缓冲器控制器（50）根据缓冲存储器（20）的内部条目数量和必要的存储体编号的数量来决定有效点（Act_point）。 缓冲器控制器（50）分离用于使用缓冲存储器（20）作为便笺式存储器的输出锁存器（40）。 存储体控制器（60）通过缓冲器控制器（50）的激活点（Act_point）以循环形式激活缓冲存储器（20）的存储体。

公开(公告)号：KR1020030068219A

公开(公告)日：2003-08-21

申请号：KR1020020007868

申请日：2002-02-14

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06T1/60 ,  G06T17/00

Abstract: PURPOSE: A texture memory access device of a three-dimensional computer graphic system is provided to improve texture mapping performance to produce more vivid three-dimensional computer graphics. CONSTITUTION: A texture memory access device of a three-dimensional computer graphic system includes a texture address aligner(210), a texture address comparator(220), a texture memory controller(230), a texture data register(240), and a texture data aligner(250). The texture address aligner receives a plurality of texture memory addresses from texture units(110) and aligns identical texture addresses. The texture address comparator compares the aligned addresses with addresses stored at the previous clock cycle to align identical texture addresses. The texture memory controller controls a texture memory using texture addresses output from the comparator. The texture data register temporarily stores data read from the texture memory. The texture data aligner realigns texture data according to control signals output from the texture address aligner and the texture address comparator to send the texture data to the texture units.

Abstract translation: 目的：提供三维计算机图形系统的纹理存储器访问装置，以提高纹理映射性能，从而产生更逼真的三维计算机图形。 构成：三维计算机图形系统的纹理存储器访问装置包括纹理地址对齐器（210），纹理地址比较器（220），纹理存储器控制器（230），纹理数据寄存器（240）和 纹理数据对齐器（250）。 纹理地址对齐器从纹理单元（110）接收多个纹理存储器地址，并对齐相同的纹理地址。 纹理地址比较器将对准的地址与前一时钟周期中存储的地址进行比较，以对齐相同的纹理地址。 纹理存储器控制器使用从比较器输出的纹理地址来控制纹理存储器。 纹理数据寄存器临时存储从纹理存储器读取的数据。 纹理数据对齐器根据从纹理地址对齐器和纹理地址比较器输出的控制信号来重新组织纹理数据，以将纹理数据发送到纹理单元。

公开(公告)号：KR1020010055517A

公开(公告)日：2001-07-04

申请号：KR1019990056733

申请日：1999-12-10

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: PURPOSE: A method for decoding a low voltage instruction for a micro processor is provided to decrease an electric power of a system by decoding a statically extracted set(SES) using a low electric power in the case that a frequently used specific program through an instruction decode look aside buffer structure is processed. CONSTITUTION: A statically extracted set(SES) comprising bits inducing an electric power consumption by generating a logic transient of an instruction decoder out of small number instruction language bits frequently used in performing of an application program in a simulation of a micro processor design stage is extracted. It is detected whether the instruction language is identified with the SES. If an instruction language is identified with the SES, a logic transient of the instruction decoder is prevented by holding a signal being connected to an instruction decode look aside buffer and a signal unnecessary for a transient of a decoder logic is extracted by generating a control signal being stored in ROM-shaped I-DLB. If an instruction language is not identified with the SES, the I-DLB is disabled, and the existing instruction decoding process is performed by making a signal being connected to an instruction decoder circuit to identify with the instruction language read from a memory.

Abstract translation: 目的：提供一种用于解码微处理器的低电压指令的方法，用于通过在通过指令的频繁使用的特定程序的情况下使用低电力对静态提取的组（SES）进行解码来降低系统的电功率 解码看待处理缓冲区结构。 构成：通过在微处理器设计阶段的仿真中在执行应用程序中频繁使用的小数量指令语言位产生指令解码器的逻辑瞬态，引起电功率消耗的静态提取组（SES）是 提取。 检测是否用SES识别指令语言。 如果使用SES标识指令语言，则通过保持连接到指令解码外部缓冲器的信号来防止指令解码器的逻辑瞬态，并且通过产生控制信号来提取对解码器逻辑的瞬态不必要的信号 存储在ROM形I-DLB中。 如果没有用SES识别指令语言，则禁止I-DLB，并且通过使信号连接到指令解码器电路来识别从存储器读取的指令语言来执行现有的指令解码处理。