公开(公告)号：KR1020030074856A

公开(公告)日：2003-09-22

申请号：KR1020020013838

申请日：2002-03-14

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F13/38

Abstract: PURPOSE: A device for controlling a buffer memory of a computer system is provided to implement a buffer system of a low-power effectively and use an internal memory as a scratch pad memory by partially activating a bank of an internal buffer memory according to a flow of the current data and the number of entry numbers of a queue and applying an adaptability in a queue system for connecting two components which create and consume data. CONSTITUTION: An output latch(40) is operated as a virtual queue when data stored in a buffer memory(20) are transmitted to a consumption component(30) or the buffer memory(20) is used as a scratch pad memory. A buffer controller(50) controls data of the buffer memory(20), and delays an operation of a processor(10) or the component(30) when an overflow or underflow of the buffer memory(20) is generated. The buffer controller(50) decides an active point(Act_point) according to the number of internal entry numbers of the buffer memory(20) and the number of necessary bank numbers. The buffer controller(50) separates an output latch(40) for using the buffer memory(20) as the scratch pad memory. A bank controller(60) activates a bank of the buffer memory(20) as a circular form by the active point(Act_point) of the buffer controller(50).

Abstract translation: 目的：提供一种用于控制计算机系统的缓冲存储器的设备，以有效地实现低功率的缓冲系统，并且通过根据流程部分地激活内部缓冲存储器组，并且使用内部存储器作为临时存储器 的当前数据和队列的入口号码，并在队列系统中应用适应性来连接创建和使用数据的两个组件。 构成：当将存储在缓冲存储器（20）中的数据传送到消耗部件（30）或缓冲存储器（20）用作暂存器存储器时，输出锁存器（40）作为虚拟队列操作。 当产生缓冲存储器（20）的上溢或下溢时，缓冲器控制器（50）控制缓冲存储器（20）的数据，并延迟处理器（10）或组件（30）的操作。 缓冲器控制器（50）根据缓冲存储器（20）的内部条目号的数量和所需的存储体号的数量来决定活动点（Act_point）。 缓冲器控制器（50）将用于使用缓冲存储器（20）的输出锁存器（40）分离为临时存储器。 银行控制器（60）通过缓冲控制器（50）的活动点（Act_point）将循环形式的缓冲存储器（20）的一行激活。

公开(公告)号：KR100465913B1

公开(公告)日：2005-01-13

申请号：KR1020030033574

申请日：2003-05-27

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F13/00

Abstract: PURPOSE: An accelerator for processing multimedia using a coprocessor on a portable system is provided to efficiently process a multimedia data stream with a small power by using a stream buffer including a system interface unit for enabling the coprocessor equipped with a program memory to directly invoke a main processor and being used as an operation register. CONSTITUTION: A coprocessor interface unit(201) connects the main processor(100) and the coprocessor(200). An internal program memory(207) stores the program. A state control unit(208) makes the coprocessor execute instructions of the main processor and requests the needed operation to the main processor. The stream buffer(203) has the system bus interface(202) for directly connecting to a system bus for the multimedia data stream, and reads/stores data on the next stream when the coprocessor performs a stream processing program. A register mapping unit(204) performs mapping in order to make the coprocessor use contents of the stream buffer as an operation register. An SIMD(Single Instruction Multiple Data) data path(206) performs an SIMD operation in order to make the coprocessor process multiple data at one instruction.

Abstract translation: 目的：提供一种用于在便携式系统上使用协处理器处理多媒体的加速器，以通过使用包括系统接口单元的流缓冲器以小功率有效地处理多媒体数据流，所述系统接口单元使得配备有程序存储器的协处理器能够直接调用 主处理器并被用作操作寄存器。 构成：协处理器接口单元（201）连接主处理器（100）和协处理器（200）。 内部程序存储器（207）存储该程序。 状态控制单元（208）使协处理器执行主处理器的指令并向主处理器请求所需的操作。 流缓冲器（203）具有用于直接连接到用于多媒体数据流的系统总线的系统总线接口（202），并且当协处理器执行流处理程序时在下一个流上读取/存储数据。 寄存器映射单元（204）执行映射以使协处理器使用流缓冲器的内容作为操作寄存器。 SIMD（单指令多数据）数据路径（206）执行SIMD操作以便使协处理器在一个指令下处理多个数据。

公开(公告)号：KR1020040079097A

公开(公告)日：2004-09-14

申请号：KR1020030014021

申请日：2003-03-06

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F17/00

Abstract: PURPOSE: A multimedia process accelerating system is provided to embed an automatic code processing function in an assistant processor, and to process a single instruction of a main processor via a memory manager so that it extends an instruction system for a multimedia process. CONSTITUTION: The system comprises a coprocessor interface unit(101), a state control unit(104), a program control unit(202), an internal program memory(201), a pipeline follower(102), a decoder(103), a stream control unit(203), a multi mode SIMD(Single Instruction Multiple Data) register file(301), an adjuster(302), an SIMD data path(105), a precision degree control unit(303), and a memory manager(205). The coprocessor interface unit(101) connects a main processor to an assistant processor. The state control unit(104) controls an overall operations of the assistant processor, and stores a current state. The program control unit(202) and the internal program memory(201) store a program for executing the assistant processor and control an execution of the assistant processor. The pipeline follower(102) synchronizes an instruction pipeline of the main processor with that of the assistant processor. The decoder(103) decodes the instruction of the main processor, and generates a control signal on an overall data path of the assistant processor. The stream control unit(203) controls a process on an multimedia data stream in a memory area. The multi mode SIMD register file(301) makes it possible setting each data value for each mode. The adjuster(302) adjusts a vector register value read from the multi mode SIMD register file(301). The SIMD data path(105) processes plural data with a single instruction. The precision degree control unit(303) adjusts a dynamic range of a calculation result. The memory manager(205) controls both the main memory and the assistant memory to access the same memory.

Abstract translation: 目的：提供一种多媒体处理加速系统，将自动代码处理功能嵌入到辅助处理器中，并通过存储器管理器处理主处理器的单个指令，从而扩展了多媒体处理的指令系统。 构成：系统包括协处理器接口单元（101），状态控制单元（104），程序控制单元（202），内部程序存储器（201），流水线跟随器（102），解码器（103） 流控制单元（203），多模式SIMD（单指令多数据）寄存器文件（301），调整器（302），SIMD数据路径（105），精度度控制单元（303） 经理（205）。 协处理器接口单元（101）将主处理器连接到辅助处理器。 状态控制单元（104）控制辅助处理器的整体操作，并存储当前状态。 程序控制单元（202）和内部程序存储器（201）存储用于执行辅助处理器的程序并控制辅助处理器的执行。 管线跟随器（102）使主处理器的指令流水线与辅助处理器的指令流水线同步。 解码器（103）解码主处理器的指令，并在辅助处理器的整个数据路径上生成控制信号。 流控制单元（203）控制存储区域中的多媒体数据流的处理。 多模式SIMD寄存器文件（301）使得可以为每个模式设置每个数据值。 调整器（302）调整从多模式SIMD寄存器文件（301）读取的向量寄存器值。 SIMD数据路径（105）用单个指令处理多个数据。 精度度控制单元（303）调整计算结果的动态范围。 存储器管理器（205）控制主存储器和辅助存储器以访问相同的存储器。

公开(公告)号：KR1020020063384A

公开(公告)日：2002-08-03

申请号：KR1020010004014

申请日：2001-01-29

Applicant: 한국과학기술원

Inventor： 유회준 ,  우람찬

IPC: G06T1/60

Abstract: PURPOSE: A memory mapping method and a virtually spanning 2D(2-Dimensional) array structure for an embedded 3D graphic accelerator are provided to use wide memory width in an EML(Embedded Memory Logic) technology, so as to enhance the performance of the embedded 3D graphic accelerator. CONSTITUTION: In a structure used in an embedded 3D graphic accelerator, processors composed of one or several two-rank layers are indirectly connected to memories through a memory interface circuit to form a physical 1D array, and another 1D array is formed according to pipelining of a first processor thereby forming virtually spanning 2D array structure. For a polygon cut to an N-by-N size, a screen is divided into N-by-1 LBs(Line Blocks). Mutually adjacent line blocks, for the divided line blocks, are mapped with mutually different memories using SALBA(Selective and Alternative Line-Block Activation) memory mapping, thereby reducing power consumption and enabling continuous and simultaneous RMW(Read-Modify-Write). And power consumption in an I/O drive is reduced according to a shape of the polygon, when reading and writing data from the memory allocated to one line block.

Abstract translation: 目的：提供嵌入式3D图形加速器的内存映射方法和实际跨越的2D（2维）阵列结构，以在EML（嵌入式存储器逻辑）技术中使用宽的存储器宽度，以提高嵌入式 3D图形加速器。 构成：在嵌入式3D图形加速器中使用的结构中，由一个或两个两级层构成的处理器通过存储器接口电路间接连接到存储器以形成物理1D阵列，并且根据流水线形成另一1D阵列 从而形成实际上跨越的2D阵列结构的第一处理器。 对于切割成N×N尺寸的多边形，屏幕被划分为N×1个LB（线块）。 使用SALBA（选择性和替代线路块激活）存储器映射，使用相互不同的存储器映射用于划分的行块的相邻线块，从而降低功耗并实现连续和同时的RMW（读 - 修改 - 写）。 当从分配给一个线路块的存储器读取和写入数据时，根据多边形的形状，I / O驱动器中的功耗被减少。

公开(公告)号：KR100463642B1

公开(公告)日：2004-12-29

申请号：KR1020030014021

申请日：2003-03-06

Applicant: 한국과학기술원

Inventor： 손주호 ,  우람찬 ,  유회준

IPC: G06F17/00

Abstract: PURPOSE: A multimedia process accelerating system is provided to embed an automatic code processing function in an assistant processor, and to process a single instruction of a main processor via a memory manager so that it extends an instruction system for a multimedia process. CONSTITUTION: The system comprises a coprocessor interface unit(101), a state control unit(104), a program control unit(202), an internal program memory(201), a pipeline follower(102), a decoder(103), a stream control unit(203), a multi mode SIMD(Single Instruction Multiple Data) register file(301), an adjuster(302), an SIMD data path(105), a precision degree control unit(303), and a memory manager(205). The coprocessor interface unit(101) connects a main processor to an assistant processor. The state control unit(104) controls an overall operations of the assistant processor, and stores a current state. The program control unit(202) and the internal program memory(201) store a program for executing the assistant processor and control an execution of the assistant processor. The pipeline follower(102) synchronizes an instruction pipeline of the main processor with that of the assistant processor. The decoder(103) decodes the instruction of the main processor, and generates a control signal on an overall data path of the assistant processor. The stream control unit(203) controls a process on an multimedia data stream in a memory area. The multi mode SIMD register file(301) makes it possible setting each data value for each mode. The adjuster(302) adjusts a vector register value read from the multi mode SIMD register file(301). The SIMD data path(105) processes plural data with a single instruction. The precision degree control unit(303) adjusts a dynamic range of a calculation result. The memory manager(205) controls both the main memory and the assistant memory to access the same memory.

Abstract translation: 目的：提供一种多媒体处理加速系统，用于将自动代码处理功能嵌入辅助处理器中，并通过存储器管理器处理主处理器的单个指令，从而扩展多媒体处理的指令系统。 该系统包括协处理器接口单元（101），状态控制单元（104），程序控制单元（202），内部程序存储器（201），流水线跟随器（102），解码器（103） 流控制单元（203），多模式SIMD（单指令多数据）寄存器文件（301），调整器（302），SIMD数据路径（105），精度控制单元（303）和存储器 经理（205）。 协处理器接口单元（101）将主处理器连接到辅助处理器。 状态控制单元（104）控制辅助处理器的整体操作，并存储当前状态。 程序控制单元（202）和内部程序存储器（201）存储用于执行辅助处理器的程序并控制辅助处理器的执行。 流水线跟随器（102）使主处理器的指令流水线与辅助处理器的指令流水线同步。 解码器（103）解码主处理器的指令，并且在辅助处理器的整个数据路径上产生控制信号。 流控制单元（203）控制存储区中的多媒体数据流的处理。 多模式SIMD寄存器文件（301）可以为每种模式设置每个数据值。 调整器（302）调整从多模式SIMD寄存器文件（301）读取的向量寄存器值。 SIMD数据路径（105）用单个指令处理多个数据。 精度控制单元（303）调整计算结果的动态范围。 存储器管理器（205）控制主存储器和辅助存储器访问相同的存储器。

公开(公告)号：KR1020040106603A

公开(公告)日：2004-12-18

申请号：KR1020030037038

申请日：2003-06-10

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06F7/52

CPC classification number: G06T15/005 ,  G06T15/04 ,  G06T2200/28

Abstract: PURPOSE: A dividing unit of a three dimensional computer graphic system is provided to eliminate MSBs(Most Significant Bits) of a dividend as many as leading zeros of a divisor when a perspective division operation needed in a texture mapping is performed. CONSTITUTION: The unit comprises a leading zero detector(110), a UV formatter(120), and a divider(130). The leading zero detector(110) receives a value of a divisor, which is a texture address value, and counts the number of the divisor. The UV formatter(120) receives values of dividends, which are also texture address values, eliminates MSBs of the dividends as many as counted zeros of the divisor or pads zeros under LSBs(Least Significant Bits) as many as the number of the eliminated ciphers. The divider(130) divides the newly formatted dividends with the divisor.

Abstract translation: 目的：提供一种三维计算机图形系统的分割单元，用于在执行纹理映射所需的透视分割操作时，消除与除数的前导零一样多的除数的MSB（最高有效位）。 构成：该单元包括前导零检测器（110），UV格式化器（120）和分隔器（130）。 前导零检测器（110）接收作为纹理地址值的除数值，并对除数的数进行计数。 UV格式化器（120）接收分红值，它们也是纹理地址值，消除除数除数除数以上的除数的MSB，或低于LSB（最低有效位）下的零点数除去密码数 。 分割器（130）将新格式化的股息与除数分开。

公开(公告)号：KR100427523B1

公开(公告)日：2004-04-28

申请号：KR1020020007868

申请日：2002-02-14

Applicant: 한국과학기술원

Inventor： 우람찬 ,  유회준

IPC: G06T1/60 ,  G06T17/00

Abstract: PURPOSE: A texture memory access device of a three-dimensional computer graphic system is provided to improve texture mapping performance to produce more vivid three-dimensional computer graphics. CONSTITUTION: A texture memory access device of a three-dimensional computer graphic system includes a texture address aligner(210), a texture address comparator(220), a texture memory controller(230), a texture data register(240), and a texture data aligner(250). The texture address aligner receives a plurality of texture memory addresses from texture units(110) and aligns identical texture addresses. The texture address comparator compares the aligned addresses with addresses stored at the previous clock cycle to align identical texture addresses. The texture memory controller controls a texture memory using texture addresses output from the comparator. The texture data register temporarily stores data read from the texture memory. The texture data aligner realigns texture data according to control signals output from the texture address aligner and the texture address comparator to send the texture data to the texture units.

Abstract translation: 目的：提供三维计算机图形系统的纹理存储器访问装置，以提高纹理映射性能，产生更生动的三维计算机图形。 3，一种三维计算机图形系统的纹理存储器访问装置，包括纹理地址对齐器（210），纹理地址比较器（220），纹理存储器控制器（230），纹理数据寄存器（240）和 纹理数据对准器（250）。 纹理地址对准器从纹理单元（110）接收多个纹理存储器地址并且对齐相同的纹理地址。 纹理地址比较器将对齐的地址与前一个时钟周期中存储的地址进行比较，以对齐相同的纹理地址。 纹理存储器控制器使用从比较器输出的纹理地址来控制纹理存储器。 纹理数据寄存器临时存储从纹理存储器读取的数据。 纹理数据对准器根据从纹理地址对准器和纹理地址比较器输出的控制信号重新对准纹理数据，以将纹理数据发送到纹理单元。

公开(公告)号：KR1020030020141A

公开(公告)日：2003-03-08

申请号：KR1020010053827

申请日：2001-09-03

Applicant: 한국과학기술원

Inventor： 우람찬 ,  윤치원 ,  국정훈 ,  이세중 ,  유회준

IPC: G06F3/14

Abstract: PURPOSE: A three dimensional computer graphics operation system is provided to install a bandwidth equalizer between a main operation processor and three dimensional computer graphics accelerators having different bandwidths for a high efficient data transmission so that it can implement a real time three dimensional computer graphics at a portable terminal. CONSTITUTION: The system comprises three dimensional computer graphics accelerators(300), a moving picture regeneration accelerator(410), and a bandwidth equalizer (200). The moving picture regeneration accelerator(410), connected to a main operation processor(100) via the bandwidth equalizer(200), accelerates a display of the three dimensional computer graphics. The three dimensional computer graphics accelerators(300) are workstation level hardwares for accelerating three dimensional graphic display with a high speed. The bandwidth equalizer(200) is a bus structure for connecting the three dimensional computer graphic accelerator(300) and the moving picture regeneration accelerator(410) to the main operation processor(100). The bandwidth equalizer(200) synchronizes the bandwidth of the three dimensional computer graphics accelerator(300) to that of the main operation processor(100) for enabling a data transmission between them. Also, the bandwidth equalizer(200) synchronizes the bandwidth of the moving picture regeneration accelerator(410) with that of the main operation processor(100).

Abstract translation: 目的：提供一种三维计算机图形操作系统，用于在具有不同带宽的主操作处理器和三维计算机图形加速器之间安装带宽均衡器，用于高效数据传输，从而可以实现三维计算机图形处理 便携式终端。 构成：该系统包括三维计算机图形加速器（300），运动图像再生加速器（410）和带宽均衡器（200）。 经由带宽均衡器（200）连接到主操作处理器（100）的运动画面再生加速器（410）加速三维计算机图形的显示。 三维计算机图形加速器（300）是用于加速高速三维图形显示的工作站级硬件。 带宽均衡器（200）是用于将三维计算机图形加速器（300）和运动图像再生加速器（410）连接到主操作处理器（100）的总线结构。 带宽均衡器（200）使三维计算机图形加速器（300）的带宽与主操作处理器（100）的带宽同步，以实现它们之间的数据传输。 此外，带宽均衡器（200）使运动图像再生加速器（410）的带宽与主运算处理器（100）的带宽同步。

公开(公告)号：KR100372090B1

公开(公告)日：2003-02-14

申请号：KR1020010004014

申请日：2001-01-29

Applicant: 한국과학기술원

Inventor： 유회준 ,  우람찬

IPC: G06T1/60

Abstract: PURPOSE: A memory mapping method and a virtually spanning 2D(2-Dimensional) array structure for an embedded 3D graphic accelerator are provided to use wide memory width in an EML(Embedded Memory Logic) technology, so as to enhance the performance of the embedded 3D graphic accelerator. CONSTITUTION: In a structure used in an embedded 3D graphic accelerator, processors composed of one or several two-rank layers are indirectly connected to memories through a memory interface circuit to form a physical 1D array, and another 1D array is formed according to pipelining of a first processor thereby forming virtually spanning 2D array structure. For a polygon cut to an N-by-N size, a screen is divided into N-by-1 LBs(Line Blocks). Mutually adjacent line blocks, for the divided line blocks, are mapped with mutually different memories using SALBA(Selective and Alternative Line-Block Activation) memory mapping, thereby reducing power consumption and enabling continuous and simultaneous RMW(Read-Modify-Write). And power consumption in an I/O drive is reduced according to a shape of the polygon, when reading and writing data from the memory allocated to one line block.

Abstract translation: 目的：提供一种用于嵌入式3D图形加速器的存储器映射方法和实际上跨越的2D（二维）阵列结构，以在EML（嵌入式存储器逻辑）技术中使用宽存储器宽度，从而提高嵌入式 3D图形加速器。 组成：在用于嵌入式3D图形加速器的结构中，由一个或几个双列层组成的处理器通过存储器接口电路间接连接到存储器以形成物理一维阵列，并且根据流水线形成另一个一维阵列 由此形成实质上跨越2D阵列结构的第一处理器。 对于切成N×N大小的多边形，屏幕被分成N×1的LB（线块）。 对于划分的行块，相互相邻的行块使用SALBA（选择性和替代性行块激活）存储器映射与相互不同的存储器映射，从而降低功耗并实现连续和同时RMW（读取 - 修改 - 写入）。 当从分配给一个行块的存储器中读取和写入数据时，根据多边形的形状减少I / O驱动器中的功耗。

公开(公告)号：KR100368132B1

公开(公告)日：2003-01-15

申请号：KR1020000015405

申请日：2000-03-27

Applicant: 한국과학기술원

Inventor： 우람찬 ,  윤치원 ,  유회준

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: A Row-After-Column memory addressing method. The memory addressing method changes the order of addressing so as to enhance the efficiency of memory addressing. The Row-After-Column memory addressing method of the present invention comprises the steps of activating a column path by generating the column address when the address is input for data access, and activating a row path by generating the row address according to the address. Therefore, pipeline stall arising from inputting the column address (/CAS) subsequent to input of the row address (/RAS) can be eliminated and the speed of memory access can be enhanced.

Abstract translation: 行后存储器寻址方法。 存储器寻址方法改变了寻址的顺序，以提高存储器寻址的效率。 本发明的行后存储器寻址方法包括以下步骤：当地址被输入用于数据访问时，通过产生列地址来激活列路径，并且通过根据地址产生行地址来激活行路径。 因此，可以消除在输入行地址（/ RAS）之后输入列地址（/ CAS）引起的流水线延迟，并且可以提高存储器访问的速度。