公开(公告)号：KR1020010063843A

公开(公告)日：2001-07-09

申请号：KR1019990061945

申请日：1999-12-24

Applicant: 한국전자통신연구원

Inventor： 장윤선 ,  문필주

IPC: H04L12/46 ,  H04L29/06 ,  H04L12/28 ,  H04B10/07 ,  H04L12/26

CPC classification number: H04L12/46 ,  H04B10/07 ,  H04L12/2885 ,  H04L43/0817 ,  H04L69/08

Abstract: PURPOSE: A PON(Passive Optical Network) slave interface device is provided to perform a subscriber optical line terminal function and interface functions of a physical layer and an ATM(Asynchronous Transfer Mode) layer. CONSTITUTION: A control processor(301) manages an interface with a CPU. A power supplying processor(302) receives a power from a main system, and supplies the power necessary for a board. A clock splitter(303) supplies clocks necessary for the board. A physical media unit(304) performs an O/E(Optical-to-Electrical) conversion or an E/O(Electrical-to-Optical) conversion. A physical layer unit(305) performs an interface with the physical media unit(304) and an ATM(Asynchronous Transfer Mode) layer unit, and manages inserting/extracting functions of ATM cells. An ONU(Optical Network Unit) integrated processor(306) performs an ATM layer processing function, a non-ATM interface function and multiplexing/reverse-multiplexing functions.

Abstract translation: 目的：提供PON（被动光网络）从接口设备，用于执行物理层和ATM（异步传输模式）层的用户光线路终端功能和接口功能。 构成：控制处理器（301）管理与CPU的接口。 电源处理器（302）从主系统接收电力，并提供电路板所需的电力。 时钟分配器（303）提供电路板所需的时钟。 物理介质单元（304）执行O / E（光电对）转换或E / O（电 - 光）转换。 物理层单元（305）与物理介质单元（304）和ATM（异步传输模式）层单元进行接口，并管理ATM信元的插入/提取功能。 ONU（光网络单元）集成处理器（306）执行ATM层处理功能，非ATM接口功能和复用/反向复用功能。

公开(公告)号：KR1020010054962A

公开(公告)日：2001-07-02

申请号：KR1019990055972

申请日：1999-12-08

Applicant: 한국전자통신연구원

Inventor： 박상조 ,  장윤선 ,  문필주 ,  이동춘

IPC: H03K17/00

CPC classification number: H04Q11/0005 ,  G02B6/2861 ,  H04Q2011/002 ,  H04Q2011/0041

Abstract: PURPOSE: A photoelectric routing circuit for low light loss and miniaturization is provided to reduce the light loss and to enable the miniaturization of the device by reducing the number of spectrometers and the number and length of photoelectric light delay lines. CONSTITUTION: In the photoelectric routing circuit, a pulse generator(200) generates very high frequencies(VHFs)(a,b,c). An external modulator(210) converts the VHFs(a,c) into photoelectric pulses. A photoelectric address generator(220) includes a photoelectric divider dividing the converted pulse into m sub sets and a photoelectric light delay line delaying the photoelectric lights divided at the photoelectric divider. An address selection signal generator includes an electric delaying the very high frequency pulse(b) generated at the pulse generator(200) and a selector selecting the output of the electric delay line. A photoelectric switch(230) switches the input from the photoelectric address generator(220) responding to the output of the address selection signal generator(240). A photoelectric OR gate(250) produces a routing address after adding the reference photoelectric signal pulse(c') converted at the external modulator(210) and the output of the photoelectric switch(230) together.

Abstract translation: 目的：提供低光损耗和小型化的光电路由电路，以减少光损耗，并通过减少光谱仪的数量和光电延迟线的数量和长度来实现器件的小型化。 构成：在光电路由电路中，脉冲发生器（200）产生非常高的频率（VHF）（a，b，c）。 外部调制器（210）将VHF（a，c）转换为光电脉冲。 光电地址发生器（220）包括将转换的脉冲分成m个子集的光电分路器和延迟在光电分配器处划分的光电光的光电延迟线。 地址选择信号发生器包括电延迟在脉冲发生器（200）产生的非常高频脉冲（b）和选择电延迟线的输出的选择器。 光电开关（230）响应于地址选择信号发生器（240）的输出，切换来自光电地址发生器（220）的输入。 光电OR门（250）在将在外部调制器（210）处转换的参考光电信号脉冲（c'）和光电开关（230）的输出相加在一起之后产生路由地址。

公开(公告)号：KR1020010054655A

公开(公告)日：2001-07-02

申请号：KR1019990055547

申请日：1999-12-07

Applicant: 한국전자통신연구원

Inventor： 이동춘 ,  문필주

IPC: G06F11/00

Abstract: PURPOSE: A method for monitoring and controlling performance of a synchronous physical layer applied in an access network is provided to supply platform configuration that is a guiding principle in implement of performance monitoring device of synchronous physical layer. CONSTITUTION: Performance data of a performance monitoring device are initialized(S111). If installation of a board is detected(S112), an error accumulative value on signal is obtained by collecting performance data through performance accumulative registers of a physical layer chip every second(S113). If new board being installed is not detected any longer(S114), the first board is set(S121). If the first board exists, performance data processing is performed by obtaining other performance elements through the error accumulative value obtained(S124). A UAS(UnAvailable Second) is decided by using the performance elements obtained from the performance data processing(S125). A critical value every 15 seconds and a day is stored. If a value of performance elements accumulated in 15 second and a day is decided to over corresponding critical value, signal is decided to be a performance drop state(S127) and the performance elements accumulated in every 15 seconds and a day is reported to a network management device periodically(S128).

Abstract translation: 目的：提供一种监控和控制接入网中应用的同步物理层性能的方法，以提供作为实现同步物理层性能监控设备的指导原则的平台配置。 规定：对性能监视装置的性能数据进行初始化（S111）。 如果检测到电路板的安装（S112），则通过每秒通过物理层芯片的性能累积寄存器收集性能数据来获得信号上的误差累积值（S113）。 如果新安装的主板不再被检测到（S114），则设置第一个电路板（S121）。 如果存在第一板，则通过获得的误差累积值获得其他性能要素来执行性能数据处理（S124）。 通过使用从演奏数据处理获得的演奏元素来决定UAS（不可用第二）（S125）。 存储每15秒和一天的临界值。 如果将在15秒和一天中累积的性能要素的值确定为超过相应的临界值，则信号被确定为性能下降状态（S127），并且每15秒和一天累积的性能要素被报告给网络 管理装置（S128）。