公开(公告)号：EP0995228A1

公开(公告)日：2000-04-26

申请号：EP98915322.6

申请日：1998-04-07

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BANDYOPADHYAY, Basab ,  GATTO, Michael, J.

IPC: H01L21/768

CPC classification number: H01L21/76811 ,  H01L21/76813

Abstract: A semiconductor process in which a semiconductor substrate (104) including a first interconnect level (108) is provided. An interlevel dielectric layer (110) is formed on the semiconductor substrate and a contact masking layer (122) is formed on the interlevel dielectric (110). A pattern of the contact masking layer (122) is aligned over a contact region (112) of the interlevel dielectric (110). An interconnect masking (130) layer is then formed on the contact masking layer (122). A pattern of the interconnect masking layer (130) is aligned over an interconnect region (136) of the interlevel dielectric layer (110). Portions of the contact region (112) are then selectively removed to form a contact tunnel (140). Portions of the interconnect region (136) are then selectively removed to form an interconnect trench (150). The contact tunnel (140) and the interconnect trench (150) are then filled with a conductive material (160). In the preferred embodiment, the contact masking layer (122) comprises a silicon nitride layer. The interconnect masking layer (130) is preferably a patterned photoresist layer formed on the contact masking layer (122). The formation of the interconnect masking layer (130) preferably precedes the step of selectively removing portions of the contact region (112) such that the interconnect masking layer (130) and the contact masking layer (122) are simultaneously present upon the interlevel dielectric layer (110) prior to the formation of the contact tunnels (140). In one embodiment, the filling of the contact tunnel and the filling of the interconnect trench are accomplished simultaneously. Ideally, selective removal of portions of the interconnect region vertically translates the contact tunnel within the interlevel dielectric such that the contact tunnel extends to an upper surface of the first interconnect level.

公开(公告)号：EP0912996A1

公开(公告)日：1999-05-06

申请号：EP97929752.0

申请日：1997-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21 ,  H01L23

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

公开(公告)号：EP0963606B1

公开(公告)日：2005-10-26

申请号：EP97907668.4

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： FULFORD, H., Jim, Jr. ,  BANDYOPADHYAY, Basab ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

公开(公告)号：EP0912996B1

公开(公告)日：2002-01-02

申请号：EP97929752.0

申请日：1997-05-27

Applicant: Advanced Micro Devices, Inc.

Inventor： BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.