公开(公告)号：WO1997038442A1

公开(公告)日：1997-10-16

申请号：PCT/US1997002438

申请日：1997-02-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  DAWSON, Robert ,  MAY, Charles, E.

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

Abstract: An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.

Abstract translation: 提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。 隔离过程产生具有增强的机械和电性能的硅台面。 通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。 通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。 图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。 图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

公开(公告)号：WO1998025182A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022616

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract translation: 掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

公开(公告)号：WO1997047036A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002513

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/768 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (12, 14), wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. The conductors and vias are made by a damascene process. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体（12,14），其中一个层上的导体相对于另一层上的导体交错。 在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。 导体和通孔由镶嵌工艺制成。 通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

公开(公告)号：WO2002075781A2

公开(公告)日：2002-09-26

申请号：PCT/US2002/002774

申请日：2002-02-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PELLERIN, John, G. ,  CHEEK, Jon, D. ,  DAWSON, Robert ,  HAUSE, Frederick, N. ,  LUNING, Scott, D.

IPC: H01L

CPC classification number: H01L29/66507 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/6653

Abstract: A transistor, comprising a semiconducting substrate (30), a gate insulation layer (48) positioned above the substrate (30), agate electrode (46) positioned above the gate insulation layer (48), a plurality of source/drain regions formed in the substrate (30), a first (40A) and a second (52) sidewall spacer positioned adjacent the gate electrode (46), and a metal silicide layer (54) formed above each of the source/drain regions, a portion of the metal silicide layer (54) being positioned adjacent the first sidewall spacer (40A) and under the second sidewall spacer (52). The method comprises forming a transistor by forming a gate insulation layer (48) and a gate electrode (46) above a semiconducting substrate (30), forming a first sidewall spacer (40A) adjacent the gate electrode (46), forming a metal silicide layer (50) adjacent the first sidewall spacer (40A) and above previously formed implant regions in the substrate, forming a second sidewall spacer (52) above a portion of the metal silicide layer (50) and adjacent the first sidewall spacer (40A), and forming additional metal silicide material (50A) above the metal silicide layer (50) extending beyond the second sidewall spacer (52).

Abstract translation: 一种晶体管，包括半导体衬底（30），位于衬底（30）上方的栅极绝缘层（48），位于栅极绝缘层（48）上方的玛瑙电极（46），多个源极/漏极区域 基板（30），邻近栅电极（46）定位的第一（40A）和第二（52）侧壁间隔物，以及形成在每个源极/漏极区域上方的金属硅化物层（54） 金属硅化物层（54）定位成邻近第一侧壁间隔物（40A）并位于第二侧壁间隔物（52）下方。 该方法包括通过在半导体衬底（30）上形成栅极绝缘层（48）和栅电极（46）来形成晶体管，形成邻近栅电极（46）的第一侧壁间隔物（40A），形成金属硅化物 邻近第一侧壁间隔物（40A）的层（50）以及衬底中先前形成的注入区域，在金属硅化物层（50）的一部分上方并邻近第一侧壁间隔物（40A）形成第二侧壁间隔物（52） 并且在金属硅化物层（50）之上形成延伸超过第二侧壁间隔物（52）的附加金属硅化物材料（50A）。

公开(公告)号：WO1998004925A2

公开(公告)日：1998-02-05

申请号：PCT/US1997005015

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Frederick, N. ,  MAY, Charles, E. ,  DAWSON, Robert

IPC: G01R00/00

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

Abstract translation: 在浅沟槽隔离器件结上使用电阻保护罩，以覆盖设备区域外围的条带之外的器件区域。 在器件的中心表面部分上形成的硅化物层和在其上防止硅化物形成的器件的周边上的条带区域形成用于评估结合形成的测试结构，其免于在器件沟槽上的硅化物形成的影响 侧壁。 将测试结构上的电气测试和泄漏测量直接与类似的硅化物浅沟槽隔离器件进行比较，该器件不包含电阻器保护掩膜和没有硅化物的浅沟槽隔离器件，以确定自对准硅化物处理是否包括结漏现象和短路 -circuiting。

公开(公告)号：WO1997047039A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002509

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  FULFORD, H., Jim, Jr. ,  BANDYOPADHYAY, Basab ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors (104) on one level are staggered with respect to conductors (106) on another level. In densely spaced interconnect areas, interposed conductors (104) are burried in intermetallic dielectric layer (103) drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括几层导体，其中一层上的导体（104）相对于另一层上的导体（106）交错排列。 在密集间隔的互连区域中，插入的导体（104）被夹在金属间介电层（103）中，拉伸到不同的高度水平以减小互连之间的电容耦合。

公开(公告)号：WO1997047035A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002510

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MICHAEL, Mark, W. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L21/0334 ,  H01L21/31051 ,  H01L21/76819

Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational (dummy) conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

Abstract translation: 提供了一种光刻掩模衍生过程，用于改善由衍生的光刻掩模形成的导体上沉积的层间电介质的整体平面性。 导出光刻掩模，使得非操作（虚拟）导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，在该导体上介质层可以沉积并容易地使其平坦化，例如， 化学机械抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体因此不对集成电路功能有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

公开(公告)号：WO1998003993A1

公开(公告)日：1998-01-29

申请号：PCT/US1997008817

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  GARDNER, Mark, L. ,  DAWSON, Robert

IPC: H01L21/768

CPC classification number: H01L21/76816

Abstract: A semiconductor process for forming an interlevel contact. A semiconductor wafer (100) is provided with a semiconductor substrate, a first conductive layer (102) formed on the substrate, and a dielectric layer (104) formed on the conductive layer. A border layer (106), preferably comprised of polysilicon nitride is formed on the dielectric layer (104). Portions of the border layer are then selectively removed to expose an upper surface region (110) of the dielectric layer, the selective removal of the border layer (106) resulting in a border layer having an annular sidewall extending upward from the dielectric layer (104) and encircling the spacer region (110). A spacer structure (116) is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure (116) thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via (128) extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer regions (110) is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via (120) at substantially less than the minimum feature size of the photolithography exposure apparatus.

Abstract translation: 一种用于形成层间接触的半导体工艺。 半导体晶片（100）设置有半导体衬底，形成在衬底上的第一导电层（102）和形成在导电层上的电介质层（104）。 在电介质层（104）上形成优选由多晶氮化物构成的边界层（106）。 然后选择性地去除边界层的部分以暴露电介质层的上表面区域（110），选择性地去除边界层（106），导致边界层具有从电介质层（104）向上延伸的环形侧壁 ）并且环绕间隔区（110）。 然后在环形侧壁上形成间隔结构（116），优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料形成间隔物结构，以在具有最小过蚀刻的平面区域中刚好清除。 间隔结构（116）由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。 然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔（128）。 优选地，基本上小于光刻曝光设备的最小特征尺寸，间隔区域（110）的横向尺寸近似等于通孔（120）的横向尺寸中的光刻曝光设备的最小特征尺寸。

公开(公告)号：WO1997043782A1

公开(公告)日：1997-11-20

申请号：PCT/US1996019801

申请日：1996-12-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MAY, Charles, E. ,  DAWSON, Robert

IPC: H01L21/321

CPC classification number: H01L21/0331 ,  G03F7/09 ,  H01L21/32139

Abstract: A method for patterning an underlying substrate includes forming a layer of spin-on glass over the substrate, forming a layer of photoresist over the spin-on glass, patterning the photoresist, patterning the spin-on glass using the photoresist as a mask, and patterning the substrate by applying an etch using the spin-on glass as a hard mask wherein the etch removes the photoresist and partially removes the spin-on glass. In one embodiment, the spin-on glass is patterned by applying a fluorine-based plasma, an aluminium-based substrate is patterned by applying a chlorine-based plasma in which an etch selectivity of the substrate to the spin-on glass is at least 10:1, and the spin-on glass is removed by applying another fluorine-based plasma.

Abstract translation: 用于图案化下面的衬底的方法包括在衬底上形成旋涂玻璃层，在旋涂玻璃上形成光致抗蚀剂层，图案化光致抗蚀剂，使用光致抗蚀剂作为掩模图案化旋涂玻璃，以及 通过使用旋涂玻璃作为硬掩模施加蚀刻图案化衬底，其中蚀刻去除光致抗蚀剂并部分地去除旋涂玻璃。 在一个实施例中，通过施加氟基等离子体来对旋涂玻璃进行图案化，通过施加氯基等离子体对基于铝的基板进行图案化，其中基板对旋涂玻璃的蚀刻选择性至少为 如图10：1所示，通过施加另一种氟基等离子体去除旋涂玻璃。

公开(公告)号：WO1997041597A1

公开(公告)日：1997-11-06

申请号：PCT/US1997003255

申请日：1997-03-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/76229

Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

Abstract translation: 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。