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    AN INTEGRATED CIRCUIT WHICH USES A DAMASCENE PROCESS FOR PRODUCING STAGGERED INTERCONNECT LINES
    1.
    发明申请
    AN INTEGRATED CIRCUIT WHICH USES A DAMASCENE PROCESS FOR PRODUCING STAGGERED INTERCONNECT LINES 审中-公开
    使用用于生产STAGGERED INTERCONNECT LINES的DAMASCENE工艺的集成电路

    公开(公告)号：WO1997047036A1

    公开(公告)日：1997-12-11

    申请号：PCT/US1997002513

    申请日：1997-02-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

    IPC: H01L21/768

    CPC classification number: H01L21/76807 ,  H01L21/768 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (12, 14), wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. The conductors and vias are made by a damascene process. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

    Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括多个级别的导体（12,14），其中一个层上的导体相对于另一层上的导体交错。 在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。 导体和通孔由镶嵌工艺制成。 通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

    SEMICONDUCTOR ISOLATION REGION BOUNDED BY A TRENCH AND COVERED WITH AN OXIDE TO IMPROVE PLANARIZATION
    2.
    发明申请
    SEMICONDUCTOR ISOLATION REGION BOUNDED BY A TRENCH AND COVERED WITH AN OXIDE TO IMPROVE PLANARIZATION 审中-公开
    半导体分离区域，由铁素体覆盖并覆盖氧化物，以改善平面化

    公开(公告)号：WO1997041597A1

    公开(公告)日：1997-11-06

    申请号：PCT/US1997003255

    申请日：1997-03-03

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

    IPC: H01L21/762

    CPC classification number: H01L21/76205 ,  H01L21/76229

    Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.

    Abstract translation: 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

    METHOD FOR FORMING SEMICONDUCTOR FIELD REGION DIELECTRICS HAVING GLOBALLY PLANARIZED UPPER SURFACES
    3.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR FIELD REGION DIELECTRICS HAVING GLOBALLY PLANARIZED UPPER SURFACES 审中-公开
    形成具有全球平面化上层表面的半导体场区电介质的方法

    公开(公告)号：WO1997039479A1

    公开(公告)日：1997-10-23

    申请号：PCT/US1997002502

    申请日：1997-02-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W.

    IPC: H01L21/3105

    CPC classification number: H01L21/76819 ,  H01L21/31055 ,  H01L21/76229

    Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.

    Abstract translation: 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。 因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。 当经受后续蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率去除较高的高度区域。 因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。 在主要在较高的高度区域进行蚀刻去除之后，剩余的填充电介质上表面被去除到与硅台面的上表面相当的水平，从而产生介于硅台面之间的单独的场电介质。 场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。 通过产生平面场电介质上表面，从形成在场电介质上或在场电介质和硅台面之间的薄膜中去除了非平面性的各种问题。

    MASK GENERATION TECHNIQUE FOR PRODUCING AN INTEGRATED CIRCUIT WITH OPTIMAL INTERCONNECT LAYOUT FOR ACHIEVING GLOBAL PLANARIZATION
    5.
    发明申请
    MASK GENERATION TECHNIQUE FOR PRODUCING AN INTEGRATED CIRCUIT WITH OPTIMAL INTERCONNECT LAYOUT FOR ACHIEVING GLOBAL PLANARIZATION 审中-公开
    用于生成集成电路的MASK生成技术与实现全球平面化的最佳互连布局

    公开(公告)号：WO1997047035A1

    公开(公告)日：1997-12-11

    申请号：PCT/US1997002510

    申请日：1997-02-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  MICHAEL, Mark, W. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  BRENNAN, William, S.

    IPC: H01L21/768

    CPC classification number: H01L21/0334 ,  H01L21/31051 ,  H01L21/76819

    Abstract: A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational (dummy) conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

    Abstract translation: 提供了一种光刻掩模衍生过程，用于改善由衍生的光刻掩模形成的导体上沉积的层间电介质的整体平面性。 导出光刻掩模，使得非操作（虚拟）导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，在该导体上介质层可以沉积并容易地使其平坦化，例如， 化学机械抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体因此不对集成电路功能有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

    INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES
    6.
    发明申请
    INTEGRATED CIRCUIT WHICH USES AN ETCH STOP FOR PRODUCING STAGGERED INTERCONNECT LINES 审中-公开
    集成电路，用于生产STAGGERED INTERCONNECT LINES

    公开(公告)号：WO1998003994A1

    公开(公告)日：1998-01-29

    申请号：PCT/US1997009452

    申请日：1997-05-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

    IPC: H01L21/768

    CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A multilevel interconnect structure (10) is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels (12) of conductors are staggered from each other (16) in separate vertical and horizontal planes. A third conductor (16) is advantageously spaced a lateral distance between at least a portion of two second conductors (26). The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

    Abstract translation: 提供了多层互连结构（10）。 多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。 导体的三个层（12）中的两个在单独的垂直和水平平面中彼此交错（16）。 第三导体（16）有利地在两个第二导体（26）的至少一部分之间隔开横向距离。 第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。 通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

    AN INTEGRATED CIRCUIT HAVING HORIZONTALLY AND VERTICALLY OFFSET INTERCONNECT LINES
    7.
    发明申请
    AN INTEGRATED CIRCUIT HAVING HORIZONTALLY AND VERTICALLY OFFSET INTERCONNECT LINES 审中-公开
    具有水平和垂直偏移互连线的集成电路

    公开(公告)号：WO1997047038A1

    公开(公告)日：1997-12-11

    申请号：PCT/US1997002329

    申请日：1997-02-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BRENNAN, William, S.

    IPC: H01L23/522

    CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (14, 16), wherein conductors (14) on one level are staggered with respect to conductors (11) on another level. Accordingly, a space (32, 34) between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics (24) which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overal intrinsic stress of the resulting intralevel and interlevel dielectric structure.

    Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括几层导体（14,16），其中一个层上的导体（14）相对于另一层上的导体（11）交错。 因此，一个级别的导体之间的空间（32,34）直接在另一个水平的导体的正上方或正下方。 交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。 此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质（24），以最小化电容耦合和传播延迟问题。 根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。 封盖电介质进一步最小化所得到的层间和层间电介质结构的内在应力。

    A MULTILEVEL INTERCONNECT STRUCTURE OF AN INTEGRATED CIRCUIT FORMED BY A SINGLE VIA ETCH AND DUAL FILL PROCESS
    8.
    发明申请
    A MULTILEVEL INTERCONNECT STRUCTURE OF AN INTEGRATED CIRCUIT FORMED BY A SINGLE VIA ETCH AND DUAL FILL PROCESS 审中-公开
    通过电流和双通道过程形成的集成电路的多路互连结构

    公开(公告)号：WO1997047034A1

    公开(公告)日：1997-12-11

    申请号：PCT/US1997002503

    申请日：1997-02-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W.

    IPC: H01L21/768

    CPC classification number: H01L21/76877

    Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors (12) on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via (24) is filled with a conductive material (30) which forms a plug separate from the material (14) used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric (22) to underlying conductors. A second dielectric (36) is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure (36) is left substantially planar in readiness for subsequent interconnect levels dielectrically deposited thereon.

    Abstract translation: 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体（12）连接到下面的层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔（24）填充有形成与用于形成互连件的材料（14）分开的插头的导电材料（30）。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通过第一电介质（22）到底层导体形成通孔。 第二电介质（36）在第一电介质上被图案化，并且用于横向地限制用于制造上覆互连的填充材料。 不管所选择的工艺顺序如何，层间电介质结构（36）保持基本平坦，以便随后在其上介电沉积的互连层。

    A FLUORINATED OXIDE LOW PERMITTIVITY DIELECTRIC STACK FOR REDUCED CAPACITIVE COUPLING
    9.
    发明申请
    A FLUORINATED OXIDE LOW PERMITTIVITY DIELECTRIC STACK FOR REDUCED CAPACITIVE COUPLING 审中-公开
    用于减少电容耦合的氟化氧化物低电容堆

    公开(公告)号：WO1997041592A1

    公开(公告)日：1997-11-06

    申请号：PCT/US1996020485

    申请日：1996-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W. ,  FULFORD, H., Jim ,  BRENNAN, William, S.

    IPC: H01L21/316

    CPC classification number: H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.

    Abstract translation: 包括在半导体衬底的形貌上形成的电介质的低介电常数层间结构。 电介质包括靠近半导体衬底的下部区域，由以约4％至10％的原子浓度掺入氟的氧化物构成的中间区域和上部区域。 形成电介质结构的方法包括在衬底上形成第一互连电平。 在由第一互连和衬底限定的形貌上形成第一电介质层，优选CVD氧化物。 然后在第一介电层上形成具有低于第一介电层的介电常数的第二电介质层。 在第二电介质层上形成第三电介质层。 第二电介质层优选地由硅烷或TEOS源形成在CVD室中，并且氟化材料例如SiF 4。

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